Thin film transistor array panel and liquid crystal display

• US 7,332,743 B2
• Filed: 09/13/2005
• Issued: 02/19/2008
• Est. Priority Date: 12/17/2004
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Hong, Mun-Pyo, Song, Keun-Kyu, Kim, Bo-Sung, Yang, Young-Chol
• Primary Examiner(s): Tran; Minhloan
• Assistant Examiner(s): Liu; Benjamin Tzu-Hung
• Application Number:
  US11/224,103
• Publication Number:
  US 20060131580A1
• Time in Patent Office: 889 Days
• Field of Search: 349/43, 349/42, 349/139, 349/143, 257/59, 257/72, 257/E27.131, 257/E27.132
• US Class Current: 257/59
• CPC Class Codes: G02F 1/133502 Antiglare, refractive index matching layers
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement

Abstract

A thin film transistor array panel is provided, which includes an insulating substrate, a gate line formed on the insulating substrate, a gate insulating layer covering the gate line, a data line formed on the gate insulating layer, a lower passivation layer covering the data line, an upper passivation layer formed on the lower passivation layer and made of organic insulating material, and a pixel electrode formed on the upper passivation layer. The thicknesses of the gate insulating layer, the lower passivation layer, and the pixel electrode are respectively represented as d_G, d_P, and d_I, the refraction indexes of the gate insulating layer, the passivation layer, and the pixel electrode are respectively represented as n_G, n_P, and n_I, and condition equations are satisfied according to: 4(d_Gn_G+d_Pn_P)=, which is an even multiple of the wavelength; and 4d_In_I=, which is an even multiple of the wavelength.

Claims

1. A thin film transistor array panel, comprising:

an insulating substrate;

a gate line formed on the insulating substrate;

a gate insulating layer covering the gate line;

a data line formed on the gate insulating layer;

a lower passivation layer covering the data line;

an upper passivation layer formed on the lower passivation layer and comprising an organic insulating material; and

a pixel electrode formed on the upper passivation layer,

wherein the gate insulating layer, the lower passivation layer, and the pixel electrode satisfy the following condition equations;

4(d_Gn_G+d_Pn_P)=which is an even multiple of a wavelength of light; and

4d_In_I=which is an even multiple of the wavelength, and,

wherein the thicknesses of the gate insulating layer, the lower passivation layer, and the pixel electrode are represented as d_G, d_P, and d_I, respectively, and the refraction index of the gate insulating layer, the passivation layer, and the pixel electrode are represented as n_G, n_p, and n_I, respectively.

2. The thin film transistor array panel of claim 1, wherein the lower passivation layer comprises a silicon nitride.

3. The thin film transistor array panel of claim 2, wherein the refraction index of the silicon nitride is between approximately 1.8-1.9.

4. The thin film transistor array panel of claim 1, wherein the refraction index of the pixel electrode is between approximately 1.8-1.9.

5. The thin film transistor array panel of claim 1, wherein the refraction index of the upper passivation layer is between approximately 1.4-1.6.

6. A liquid crystal display, comprising:

a first substrate;

a gate insulating layer formed on the first substrate;

a lower passivation layer formed on the gate insulating layer;

an upper passivation layer formed on the lower passivation layer and comprising an organic insulating material;

a pixel electrode formed on the upper passivation layer;

a second substrate facing the first substrate; and

a liquid crystal layer formed between the first substrate and the second substrate,

wherein the gate insulating layer, the lower passivation layer, and the pixel electrode satisfy the following condition equations;

4(d_Gn_G+d_pn_p)=which is an even multiple of a wavelength of light, and

4d₁n₁=which is an even multiple of the wavelength, and

wherein the thicknesses of the gate insulating layer, the lower passivation layer, and the pixel electrode are represented as d_G, d_p, and d₁, respectively, and the refraction index of the gate insulating layer, the passivation layer, and the pixel electrode are represented as n_G, n_p, and n₁, respectively.