Trench-gate semiconductor devices

• US 7,332,771 B2
• Filed: 04/10/2003
• Issued: 02/19/2008
• Est. Priority Date: 04/18/2002
• Status: Expired due to Fees

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Peake, Steven T.
• Primary Examiner(s): Lee, Eugene
• Application Number:
  US10/511,212
• Publication Number:
  US 20050173757A1
• Time in Patent Office: 1,776 Days
• Field of Search: 257328-330, 257/E27.091
• US Class Current: 257/329
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench-gate vertical power transistor in which the trench-gates (11) are parallel stripes which extend across the active area (100). Source regions (13) and ruggedness regions (15) extend to a source contact surface as alternating stripe areas having a width perpendicular to and fully between each two adjacent parallel stripe trench-gates (11). The ruggedness regions (15) are more heavily doped than the source regions and this enables an increased length of the source regions with a consequent reduction in specific resistance of the transistor. For example, the mesa width (13,15) and the trench-gate (11) width may both be about 0.4 μm, the ruggedness region (15) length may be about 1 μm and the source region (13) length may be about 20 μm. The doping concentration of the p type ruggedness regions (15) may be approximately 10 times greater than the doping concentration of the n type regions (13), for example about 10₂₁ cm₋₃ and about 10₂₀ cm₋₃ respectively.

Claims

1. A vertical power transistor trench-gate semiconductor device comprising a semiconductor body having an active area with a plurality of electrically parallel transistor cells, wherein trench-gates in the active area each comprise a trench extending into the semiconductor body with gate material in the trench, wherein the transistor cells have source and drain regions or a first conductivity type which are separated by a channel-accommodating region of a second, opposite, conductivity type adjacent a trench-gate, wherein ruggedness regions are provided which are localised regions of the second conductivity type but which are more heavily doped than the channel-accommodating regions and which extend into the drain region, wherein the trench-gates are parallel stripes which each extend across the active area, wherein the source regions and the ruggedness regions extend to a source contact surface of the semiconductor body as alternating stripe areas having a width perpendicular to and fully between each of two adjacent parallel stripe trench-gates, and wherein the device is characterized by the ruggedness regions being more heavily doped than the source regions.

2. A power transistor device as claimed in claim 1, wherein the cell pitch, that is the width of the source and ruggedness region stripes (mesa width) plus the width of an adjacent trench-gate stripe, is less than 2 μ

m, and wherein the length of the source region stripes is in the range of 10 μ

m to 50 μ

m.

3. A power transistor device as claimed in claim 2, wherein the cell pitch is in the range of 0.5 μ

m to 1.5 μ

m.

4. A power transistor device as claimed in claim 2, wherein the mesa width is approximately equal to the trench-gate stripe width.

5. A power transistor device as claimed in claim 2, wherein the length of the source region stripes is in the range 10 μ

m to 30 μ

m.

6. A power transistor device as claimed in claim 5, wherein the length of the source region stripes is approximately 20 μ

m.

7. A power transistor device as claimed in claim 2, wherein the length of the ruggedness region stripes is not greater than about 1 μ

m.

8. A power transistor device as claimed in claim 2, wherein the ratio of the length of the source region stripes to the length of the ruggedness region stripes is in the range 10 to 30.

9. A power transistor device as claimed in claim 8, wherein the ratio of the source region stripe length to ruggedness region stripe length is about 20.

10. A power transistor device as claimed in claim 1, wherein the semiconductor body is silicon, wherein the ruggedness regions have p-type conductivity with a doping concentration in the range of 10¹⁹ cm⁻

3 to 10²² cm<sup>−

3</sup>, and wherein the source regions have n-type conductivity with a doping concentration in the range of 10¹⁸ cm<sup>−

3</sup> to 10²¹ cm<sup>−

3</sup>.

11. A power transistor device as claimed in claim 1, wherein the doping concentration of the ruggedness regions is approximately 10 times greater than the doping concentration of the source regions.

12. A power transistor device as claimed in claim 11, wherein the doping concentration of the ruggedness regions is about 10²¹ cm ⁻

3 and the doping concentration of the source regions is about 10²⁰ cm<sup>−

3</sup>.

13. A power transistor device as claimed in claim 1, wherein the ruggedness regions extend further into the drain region than the trench-gates.

14. A power transistor device as claimed in claim 1, wherein the drain-source breakdown voltage of the device is in the range up to about 50 volts.

15. A vertical power transistor trench-gate semiconductor device comprising a semiconductor body having an active area with a plurality of electrically parallel transistor cells, wherein trench-gates in the active area each comprise a trench extending into the semiconductor body with gate material in the trench, wherein the transistor cells have source and drain regions of a first conductivity type which are separated by a channel-accommodating region of a second, opposite, conductivity type adjacent a trench-gate, wherein ruggedness regions are provided which are localised regions of the second conductivity type but which arc more heavily doped than the channel-accommodating regions and which extend into the drain region, wherein the trench-gates are parallel stripes which each extend across the active area, wherein the source regions and the ruggedness regions extend to a source contact surface of the semiconductor body as alternating stripe areas having a width perpendicular to and fully between each of two adjacent parallel stripe trench-gates, and wherein the device is characterized by the ruggedness regions being more heavily doped than the source regions, and wherein the length of the ruggedness regions is less than the length of the source regions, and wherein a distance between two immediately adjacent channel-accommodating regions equals the width of the source regions.