Inverter, semiconductor logic circuit, static random access memory and data latch circuit

• US 7,332,780 B2
• Filed: 03/04/2003
• Issued: 02/19/2008
• Est. Priority Date: 07/09/2002
• Status: Active Grant

• Current Assignee: Japan Aerospace Exploration Agency
• Original Assignee: Japan Aerospace Exploration Agency
• Inventors: Matsuda, Sumio, Deguchi, Yasushi, Kuboyama, Satoshi
• Primary Examiner(s): Purvis; Sue A.
• Assistant Examiner(s): Erdem; Fazli
• Application Number:
  US10/377,884
• Publication Number:
  US 20040007743A1
• Time in Patent Office: 1,813 Days
• Field of Search: 257/367, 257/368, 257/369, 257/370, 257/366, 257/365, 257/903, 257/205, 257/206, 365/95, 327/277, 327/208, 327/210
• US Class Current: 257/369
• CPC Class Codes: G11C 11/4125 Cells incorporating circuit means for protecting against loss of information
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H03K 17/08142 in field-effect transistor switches
• CPC Class Codes: H03K 19/00338 In field effect transistor circuits
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

A dual structure is introduced to the transistor in a flip-flop or a data input step controlled by a clock of a semiconductor logic circuit. The dual structure is formed by connecting a transistor with a MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain and connecting their gates to each other, or by connecting an inverter with p-MOS transistors, one for VDD side and one for VSS side of the output step. The dual structure prevents single event phenomenon in a semiconductor logic circuit, such as inverter, SRAM and data latch circuit.

Claims

1. An inverter having a structure that a first p-channel MOS transistor and a first n-channel MOS transistor are connected in this order in series with respect to the line of a source or drain and from the node connected on the side of the first power supply to the node connected on the side of the second power supply, wherein:

said first p-channel MOS transistor constitutes a dual structure by being connected with a second p-channel MOS transistor in series with respect to the line of a source or drain at the node on the side of the second power supply, and their gates being connected to each other, and

said first n-channel MOS transistor constitutes a dual structure by being connected with a third p-channel MOS transistor in series with respect to the line of a source or drain at the node on the side of the first power supply, and the gate of the third p-channel MOS transistor being connected in common to the node of said n-channel MOS transistor on the side of the first power supply and the node of said first p-channel MOS transistor on the side of the second power supply, wherein the connection of the gates defines an input.

2. An inverter in which a first p-channel MOS transistor, a second p-channel MOS transistor, a third p-channel MOS transistor and an n-channel MOS transistor, each of which constitutes an inverter, are connected in this order in series with respect to the line of a source or drain and from the node connected on the side of a first power supply to the node connected on the side of a second power supply, wherein:

the gates of said first p-channel MOS transistor, said second p-channel MOS transistor and said n-channel MOS transistor are connected in common and are connected to the input of said inverter,

the gate of said third p-channel MOS transistor is connected to the node between said third p-channel MOS transistor and said n-channel MOS transistor with respect to the line of a source or drain, and in common to the node between said first p-channel MOS transistor and said second p-channel transistor with respect to the line of a source or drain,

the node between said second p-channel MOS transistor and said third p-channel MOS transistor on the line of a source or drain is connected to the output of said inverter,

said first p-channel MOS transistor and said second p-channel MOS transistor form a p-channel MOS transistor having a dual structure, and

said third p-channel MOS transistor and said n-channel MOS transistor form an n-channel MOS transistor having a dual structure.

3. An inverter having a structure that a first p-channel MOS transistor and a first n-channel MOS transistor are connected in this order in series with respect to the line of a source or drain and from the node connected to the side of the first power supply to the node connected to the side of the second power supply, wherein:

at least one of said first p-channel MOS transistor and said first n-channel MOS transistor constitutes a dual structure by being connected with a second MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain, and their gates being connected to each other, and

the domain of the source and drain of two MOS transistors contained in the MOS transistor having said dual structure are positioned along a single line.

5. The inverter of claim 3, wherein said predetermined space between the gates is between 2 μ

m and 8 μ

m.

6. The inverter of claim 3, wherein said predetermined space between the gates is between 2 μ

m and 5 μ

m.

4. An inverter having a structure that a first p-channel MOS transistor and a first n-channel MOS transistor are connected in this order in series with respect to the line of a source or drain and from the node connected to the side of the first power supply to the node connected to the side of the second power supply, wherein:

at least one of said first p-channel MOS transistor and said first n-channel MOS transistor constitutes a dual structure by being connected with a second MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain, and their gates being connected to each other, and

two MOS transistors contained in the MOS transistor having said dual structure are positioned by spacing a predetermined space between the gates of each other.

7. A semiconductor logic circuit comprising two inverters cross-connected to each other by connecting the output of one to the input of the other, wherein:

at least one inverter of said inverters is an inverter having a structure that a first p-channel MOS transistor and a first n-channel MOS transistor are connected in this order in series with respect to the line of a source or drain and from the node connected to the side of the first power supply to the node connected to the side of the second power supply, wherein;

at least one of said first p-channel MOS transistor and said first n-channel MOS transistor constitutes a dual structure by being connected with a second MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain, and their gates being connected to each other; and

two MOS transistors contained in the MOS transistor having said dual structure are positioned by spacing a predetermined space between each other'"'"'s gates.

8. A static random access memory comprising two inverters cross-connected to each other by connecting the output of one to the input of the other, wherein:

at least one inverter of said inverters is an inverter having a structure that a first p-channel MOS transistor and a first n-channel MOS transistor are connected in this order in series with respect to the line of a source or drain and from the node connected to the side of the first power supply to the node connected to the side of the second power supply, wherein;

at least one of said first p-channel MOS transistor and said first n-channel MOS transistor constitutes a dual structure by being connected with a second MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain, and their gates being connected to each other; and

two MOS transistors contained in the MOS transistor having said dual structure are positioned by spacing a predetermined space between each other'"'"'s gates.

9. A data latch circuit comprising two inverters cross-connected to each other by connecting the output of one to the input of the other where the output of one of said inverters is connected to the input of the other of said inverters under the control of the inverted logic signal of the clock signal for control, wherein:

at least one inverter of said inverters is an inverter having a structure that a first p-channel MOS transistor and a first n-channel MOS transistor are connected in this order in series with respect to the line of a source or drain and from the node connected to the side of the first power supply to the node connected to the side of the second power supply, wherein;

at least one of said first p-channel MOS transistor and said first n-channel MOS transistor constitutes a dual structure by being connected with a second MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain, and their gates being connected to each other; and

two MOS transistors contained in the MOS transistor having said dual structure are positioned by spacing a predetermined space between each other'"'"'s gates.

10. A semiconductor logic circuit comprising a CMOS switch in which a data signal is connected to one terminal and said data signal is output from the other terminal to a downstream under the control of the clock signal for control, wherein:

at least one MOS transistor of the p-channel MOS transistor and the n-channel MOS transistor contained in said CMOS switch whose gate is connected to said clock signal for control constitutes a dual structure by being connected with a MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain, and their gates being connected to each other, and

two MOS transistors contained in the MOS transistor having said dual structure are connected, via the line of a source or drain of MOS transistor whose gate is connected to said data signal, in series with respect to the line of a source or drain.

11. A semiconductor logic circuit comprising a CMOS switch in which a data signal is connected to one terminal and said data signal is output from the other terminal to a downstream under the control of the clock signal for control, wherein:

at least one MOS transistor of the p-channel MOS transistor and the n-channel MOS transistor contained in said CMOS switch whose gate is connected to said clock signal for control constitutes a dual structure by being connected with a MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain, and their gates being connected to each other, and

said semiconductor logic circuit is a data latch circuit which further comprises;

the second inverter whose input is connected to said signal output to a downstream, and

the third inverter, which is controlled by complementary clock signals of logic functionally contrary to said clock signal for control, whose input is connected to the output of said second inverter, and whose output is connected to the input of said second inverter.

12. A semiconductor logic circuit comprising a CMOS switch in which a data signal is connected to one terminal and said data signal is output from the other terminal to a downstream under the control of the clock signal for control, wherein:

at least one MOS transistor of the p-channel MOS transistor and the n-channel MOS transistor contained in said CMOS switch whose gate is connected to said clock signal for control constitutes a dual structure by being connected with a MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain, and their gates being connected to each other, and

the domain of the source and drain of two MOS transistors contained in the MOS transistor having said dual structure are positioned along a single line.

13. A semiconductor logic circuit comprising a CMOS switch in which a data signal is connected to one terminal and said data signal is output from the other terminal to a downstream under the control of the clock signal for control, wherein:

at least one MOS transistor of the p-channel MOS transistor and the n-channel MOS transistor contained in said CMOS switch whose gate is connected to said clock signal for control constitutes a dual structure by being connected with a MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain, and their gates being connected to each other, and

two MOS transistors contained in the MOS transistor having said dual structure are positioned by spacing a predetermined space between the gates of each other.

14. The semiconductor logic circuit of claim 13, wherein said predetermined space between the gates is between 2 μ

m and 8 μ

m.

15. The semiconductor logic circuit of claim 13, wherein said predetermined space between the gates is between 2 μ

m and 5 μ

m.

16. A semiconductor logic circuit comprising a first inverter in which a data signal is connected to the input and an inverted logic signal of said data signal is output to a downstream under the control of the complementary clock signals for control, wherein:

at least one MOS transistor of the p-channel MOS transistor and the n-channel MOS transistor contained in said first inverter whose gate is connected to said complementary clock signal for control constitutes a dual structure by being connected with a MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain, and their gates being connected to each other, and

two MOS transistors contained in the MOS transistor having said dual structure are connected, via the line of a source or drain of MOS transistor whose gate is connected to said data signal, in series with respect to the line of a source or drain.

17. A semiconductor logic circuit comprising a first inverter in which a data signal is connected to the input and an inverted logic signal of said data signal is output to a downstream under the control of the complementary clock signals for control, wherein:

at least one MOS transistor of the p-channel MOS transistor and the n-channel MOS transistor contained in said first inverter whose gate is connected to said complementary clock signal for control constitutes a dual structure by being connected with a MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain, and their gates being connected to each other, and

said semiconductor logic circuit is a data latch circuit which further comprises;

the second inverter whose input is connected to said signal output to a downstream, and

the third inverter, which is controlled by a complementary clock signal of logic contrary to said complementary clock signal for control, whose input is connected to the output of said second inverter, and whose output is connected to the input of said second inverter.

18. A semiconductor logic circuit comprising a first inverter in which a data signal is connected to the input and an inverted logic signal of said data signal is output to a downstream under the control of the complementary clock signals for control, wherein:

at least one MOS transistor of the p-channel MOS transistor and the n-channel MOS transistor contained in said first inverter whose gate is connected to said complementary clock signal for control constitutes a dual structure by being connected with a MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain, and their gates being connected to each other, and

the domain of the source and drain of two MOS transistors contained in the MOS transistor having said dual structure are positioned along a single line.

19. A semiconductor logic circuit comprising a first inverter in which a data signal is connected to the input and an inverted logic signal of said data signal is output to a downstream under the control of the complementary clock signals for control, wherein:

at least one MOS transistor of the p-channel MOS transistor and the n-channel MOS transistor contained in said first inverter whose gate is connected to said complementary clock signal for control constitutes a dual structure by being connected with a MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain, and their gates being connected to each other, and

two MOS transistors contained in the MOS transistor having said dual structure are positioned by spacing a predetermined space between the gate of each other.

20. The semiconductor logic circuit of claim 19, wherein said predetermined space between the gates is between 2 μ

m and 8 μ

m.

21. The semiconductor logic circuit of claim 19, wherein said predetermined space between the gates is between 2 μ

m and 5 μ

m.

22. A data latch circuit comprising:

a first data latch circuit which comprises a first inverter (11I1), a second inverter (11I2), a first CMOS switch (11S1) in which a data signal is connected to one terminal and said data signal is output from the other terminal to a downstream under the control of the clock signal for control, and a second CMOS switch (11S2) in which the output of said second inverter is connected to one terminal and the data signal input from said one terminal is output from the other terminal to a downstream under the control of the inverted logic signal of said clock signal; and

a second data latch circuit which comprises a third inverter (11I3), a fourth inverter (11I4), a third CMOS switch (11S3) in which said data signal is connected to one terminal and said data signal is output from the other terminal to a downstream under the control of said clock signal for control, and a fourth CMOS switch (11S4) in which the output of said fourth inverter is connected to one terminal and the data signal input from said one terminal is output from the other terminal to a downstream under the control of the inverted logic signal of said clock signal,

wherein;

each of said first, second, third and fourth inverters comprises a p-channel MOS transistor and an n-channel MOS transistor connected in series with respect to the line of a source or drain;

the output of said first inverter is connected to the gate of the transistor having one conductivity type of said second inverter and to the gate of the transistor having said one conductivity type of said fourth inverter;

the output of said third inverter is connected to the gate of the transistor having the other conductivity type of said second inverter and to the gate of the transistor having said other conductivity type of said fourth inverter;

the output of said second inverter is connected, via said second CMOS switch, to the gate of the transistor having one conductivity type of said first inverter and to the gate of the transistor having said one conductivity type of said third inverter;

the output of said fourth inverter is connected, via said fourth CMOS switch, to the gate of the transistor having the other conductivity type of said first inverter and to the gate of the transistor having said other conductivity type of said third inverter;

the output from said other terminal of said first CMOS switch is connected to the output from said other terminal of said second CMOS switch, to the gate of the transistor having said one conductivity type of said first inverter and to the gate of the transistor having said one conductivity type of said third inverter; and

the output from said other terminal of said third CMOS switch is connected to the output from said other terminal of said fourth CMOS switch, to the gate of the transistor having said other conductivity type of said first inverter and to the gate of the transistor having said other conductivity type of said third inverter.

23. The data latch circuit of claim 22, wherein:

the inverter of said first to fourth inverters comprises a p-channel MOS transistor and an n-channel MOS transistor, in which the drive performance of one MOS transistor is larger than the drive performance of the other MOS transistor;

when the drive performance of said p-channel MOS transistor is larger than the drive performance of said n-channel transistor, the output of said inverter is connected, either directly or via a CMOS switch, to the gates of p-channel MOS transistors included in each of the inverters contained, between the combination of the first and the third inverters and the combination of the second and the fourth inverters, in the combination of the inverters which does not include said inverter; and

when the drive performance of said n-channel MOS transistor is larger than the drive performance of said p-channel transistor, the output of said inverter is connected, either directly or via a CMOS switch, to the gates of n-channel MOS transistors included in each of the inverters contained, between the combination of the first and the third inverters and the combination of the second and the fourth inverters, in the combination of the inverters which does not include said inverter.