Poly-phase frequency synthesis oscillator
First Claim
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1. A circuit, comprising:
- a reference clock providing a reference clock signal operating at a reference frequency; and
a poly-phase frequency multiplier coupled with the reference clock signal, the poly-phase frequency multiplier providing an output signal with an output frequency that is a multiple M of the reference frequency, the poly-phase frequency multiplier having;
an input bias stage,a poly-phase filter stage generating a plurality of phases of the reference clock signal, the plurality of phases numbering 2*M phases separated by a phase difference of 360/(2*M) degrees, anda logic stage configured to receive the 2*M phases from the poly-phase filter stage and generate the output signal having the output frequency therefrom.
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Abstract
A frequency synthesis/multiplication circuit and method for multiplying the frequency of a reference signal. In one embodiment, multiple versions of the reference signal are generated having different phases relative to one another, and these multiple versions are combined to form an output signal having a frequency that is a multiple of the frequency of the reference signal.
67 Citations
20 Claims
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1. A circuit, comprising:
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a reference clock providing a reference clock signal operating at a reference frequency; and a poly-phase frequency multiplier coupled with the reference clock signal, the poly-phase frequency multiplier providing an output signal with an output frequency that is a multiple M of the reference frequency, the poly-phase frequency multiplier having; an input bias stage, a poly-phase filter stage generating a plurality of phases of the reference clock signal, the plurality of phases numbering 2*M phases separated by a phase difference of 360/(2*M) degrees, and a logic stage configured to receive the 2*M phases from the poly-phase filter stage and generate the output signal having the output frequency therefrom. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A circuit for multiplying a frequency of a reference signal, comprising:
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an input bias stage coupled with the reference signal and generating a biased reference signal; a filter stage receiving the biased reference signal, the filter stage generating a plurality of delayed signals derived from the reference signal; and a logic stage receiving the plurality of delayed signals and generating an output signal having an output frequency that is a multiple M of the frequency of the reference signal; wherein said plurality of delayed signals are 2*M signals each separated by a phase difference of 360/(2*M) degrees. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. A method for multiplying a frequency of a reference signal by a multiple M, comprising:
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receiving a reference signal from a reference signal source; generating multiple versions of the reference signal numbering 2*M at a frequency multiplier coupled to the reference signal source, each of said multiple versions having a different phase 360/(2*M) degrees than at least two others of said multiple versions; and combining said multiple versions of the reference signal to form an output signal having a frequency that is the multiple M of the frequency of the reference signal.
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Specification