Cell-downgrading and reference-voltage adjustment for a multi-bit-cell flash memory
First Claim
1. A downgradable cell-density flash-memory system comprising:
- a flash memory arranged as blocks of multiple pages, wherein pages are written and blocks are erased, wherein individual pages are not individually erasable except by erasing all pages in the block;
multi-level memory cells in the flash memory that each store B logical bits per cell, wherein the multi-level memory cells each store charge in one of 2B levels to represent the B logical bits;
a bit line coupled to a selected cell in the multi-level memory cells;
a plurality of references generated from a first reference, the plurality of references being in a sequence of differing values;
a plurality of comparators that generate a plurality of compare results by comparing the bit line to the plurality of references;
translation logic that receives the compare results as inputs, and generates B read data bits for the selected cell;
a bits-per-cell indicator stored for a selected block of the multi-level memory cells, the selected block containing the selected cell, the bits-per-cell indicator indicating when the selected cell stores B logical bits, and when the selected cell stores a downgraded number D of logical bits less than B logical bits;
first downgrade logic, responsive to the bits-per-cell indicator, for blocking a least-significant of the B read data bits when the bits-per-cell indicator indicates that the selected cell stores D=B−
1 logical bits; and
second downgrade logic, responsive to the bits-per-cell indicator, for blocking a second least-significant of the B read data bits when the bits-per-cell indicator indicates that the selected cell stores D=B−
2 logical bits;
wherein B, D are whole numbers and B is at least 3;
whereby least-significant bits in the B logical bits are blocked when the selected cell is downgraded by the bits-per-cell indicator.
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Abstract
A flash memory has multi-level cells (MLC) that can each store multiple bits per cell. Blocks of cells can be downgraded to fewer bits/cell when errors occur, or for storing critical data such as boot code. The bits from a single MLC are partitioned among multiple pages to improve error correctability using Error Correction Code (ECC). An upper reference voltage is generated by a voltage reference generator in response to calibration registers that can be programmed to alter the upper reference voltage. A series of decreasing references are generated from the upper reference voltage and are compared to a bit-line voltage. Compare results are translated by translation logic that generates read data and over- and under-programming signals. Downgraded cells use the same truth table but generate fewer read data bits. Noise margins are asymmetrically improved by using the same sub-states for reading downgraded and full-density MLC cells.
92 Citations
20 Claims
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1. A downgradable cell-density flash-memory system comprising:
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a flash memory arranged as blocks of multiple pages, wherein pages are written and blocks are erased, wherein individual pages are not individually erasable except by erasing all pages in the block; multi-level memory cells in the flash memory that each store B logical bits per cell, wherein the multi-level memory cells each store charge in one of 2B levels to represent the B logical bits; a bit line coupled to a selected cell in the multi-level memory cells; a plurality of references generated from a first reference, the plurality of references being in a sequence of differing values; a plurality of comparators that generate a plurality of compare results by comparing the bit line to the plurality of references; translation logic that receives the compare results as inputs, and generates B read data bits for the selected cell; a bits-per-cell indicator stored for a selected block of the multi-level memory cells, the selected block containing the selected cell, the bits-per-cell indicator indicating when the selected cell stores B logical bits, and when the selected cell stores a downgraded number D of logical bits less than B logical bits; first downgrade logic, responsive to the bits-per-cell indicator, for blocking a least-significant of the B read data bits when the bits-per-cell indicator indicates that the selected cell stores D=B−
1 logical bits; andsecond downgrade logic, responsive to the bits-per-cell indicator, for blocking a second least-significant of the B read data bits when the bits-per-cell indicator indicates that the selected cell stores D=B−
2 logical bits;wherein B, D are whole numbers and B is at least 3; whereby least-significant bits in the B logical bits are blocked when the selected cell is downgraded by the bits-per-cell indicator. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for downgrading multi-level memory cells in a flash memory comprising:
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reading a bits-per-cell indicator for a block of the multi-level memory cells to determine a number of logical bits stored in each of the multi-level memory cells; reading data from the multi-level memory cells by comparing a bit-line voltage driven by a selected cell in the multi-level memory cells to a plurality of reference voltage levels; determining when an error occurs while reading the data from the multi-level memory cells; relocating data in the block to a new block when the error occurs; when the bits-per-cell indicator for the block is at a minimum density of 1 bit per cell and the error is detected, marking the block as a bad block after the data in the block is relocated; reducing a value of the bits-per-cell indicator for the block to generated a downgraded value when the error is detected and the data in the block is relocated; writing the downgraded value to the bits-per-cell indicator for the block; and writing new data to the block wherein a number of logical bits stored in each of the multi-level memory cells in the block is the downgraded value; whereby the block is downgraded to the downgraded value of logical bits per cell when the error occurs. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A downgradable flash memory with multi-level memory cells comprising:
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multi-level-cell (MLC) flash memory means for storing multiple bits of data per multi-level memory cell, arranged as blocks of multiple pages, wherein pages are written and blocks are erased, wherein individual pages are not individually erasable except by erasing all pages in the block; bits-per-cell indicator means for indicating a number of logical bits stored in each of the multi-level memory cells in the block; voltage compare means for comparing a bit-line voltage driven by a selected cell in the multi-level memory cells to a plurality of reference voltage levels to generate compare results; error detect means for determining when an error occurs while reading the data from the multi-level memory cells; relocate means for relocating data in the block to a new block when the error occurs; bad block means for marking the block as a bad block after the data in the block is relocated when the bits-per-cell indicator means for the block is at a minimum density of 1 bit per cell and the error is detected, cell downgrade means for reducing a value of the bits-per-cell indicator means for the block to generated a downgraded value when the error is detected and the data in the block is relocated; reduced cell-density write means for writing new data to the block wherein a number of logical bits stored in each of the multi-level memory cells in the block is the downgraded value; whereby the block is downgraded to the downgraded value of logical bits per cell when the error occurs. - View Dependent Claims (18, 19, 20)
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Specification