Method and apparatus for metadata synchronization

• US 7,333,725 B1
• Filed: 03/24/2005
• Issued: 02/19/2008
• Est. Priority Date: 03/24/2005
• Status: Expired due to Fees

• Current Assignee: L-3 Communications Corporation (L3Harris Technologies, Inc.)
• Original Assignee: L-3 Communications Sonoma EO, Inc. (L3Harris Technologies, Inc.)
• Inventors: Frazier, Brian E
• Primary Examiner(s): PERKEY, WILLIAM B
• Application Number:
  US11/090,948
• Time in Patent Office: 1,062 Days
• Field of Search: 396/182, 396/187, 396/240, 396263-265, 396/325, 396332-333, 396/335, 396/377, 396/406, 348/495, 348/521, 348/64, 348/207.99, 348/207.11, 348/211.11, 377 1- 2, 377/20, 377/130, 375/355, 375/376, 353/84, 356/436, 703/19, 713/375, 713400-401, 713501-502, 710/9, 710/58, 712/2, 712/9, 712/10, 709/205, 709/248, 709/225
• US Class Current: 396/263
• CPC Class Codes: G03B 31/04 in which sound track is not on, but is synchronised with, a moving-picture film
• CPC Class Codes: H04N 1/00251 with an apparatus for taking photographic images, e.g. a camera
• CPC Class Codes: H04N 1/00278 with a printing apparatus, e.g. a laser beam printer
• CPC Class Codes: H04N 23/66 Remote control of cameras or camera parts, e.g. by remote control devices

Abstract

A method and apparatus provides for accurately synchronizing a plurality of sensors, as well as for providing accurate timing information (e.g. timing metadata) associated with the synchronized data capture. According to one aspect of the invention, an apparatus includes a synchronization circuit that stores a counter having a value corresponding to the delay characteristics of an associated sensor. The counter is used to provide a synchronization pulse to the associated sensor which is offset from a desired synchronization time by an amount that will compensate for the delay characteristics. In one example, one counter is provided for each associated sensor, allowing a high degree of accuracy in synchronization among a plurality of sensors. According to another aspect of the invention, the synchronization pulses are locked onto and derived from a pulse received from a GPS receiver. The GPS receiver is also used to mark time associated with the generated synchronization pulses, and thus obtain highly accurate time information (e.g. metadata) associated with the synchronization pulses provided to the sensors.

Claims

1. A timing apparatus comprising:

a first synchronization counter that receives a system clock and a pre-trigger, the first synchronization counter generating a first synchronization signal that is offset from the pre-trigger based on a first count of the system clock and a first delay characteristic, the first synchronization signal triggering a first data capture time; and

a second synchronization counter that receives the system clock and the pre-trigger, the second synchronization counter generating a second synchronization signal different from the first synchronization signal and that is offset from the pre-trigger based on a second count of the system clock and a second delay characteristic, the second synchronization signal triggering a second data capture time,

wherein the respective offsets of the first and second synchronization signals from the common pre-trigger compensate for the respective first and second delay characteristics and cause the first and second data capture times to occur at substantially the same absolute time.

2. A timing apparatus according to claim 1, wherein the first and second delay characteristics are associated with first and second sensors that receive the first and second synchronization signals, respectively.

3. A timing apparatus according to claim 1, wherein the first and second counts have a resolution of less than 50 nanoseconds.

4. A timing apparatus according to claim 1, further comprising a divider circuit that generates the pre-trigger based on a desired frame rate.

5. A timing apparatus according to claim 2, further comprising a divider circuit that generates the pre-trigger based on a desired frame rate.

6. A timing apparatus according to claim 4, wherein the divider circuit generates the pre-trigger by dividing the system clock.

7. A timing apparatus according to claim 5, wherein the divider circuit generates the pre-trigger by dividing the system clock.

8. A timing apparatus according to claim 1, further comprising first and second pre-load registers for storing count values corresponding to the first and second delay characteristics, respectively, the first and second synchronization circuits using the count values to compare to the first and second counts of the system clock in determining when to generate the first and second synchronization signals, respectively.

9. A timing apparatus according to claim 2, further comprising first and second pre-load registers for storing count values corresponding to the first and second delay characteristics, respectively, the first and second synchronization circuits using the count values to compare to the first and second counts of the system clock in determining when to generate the first and second synchronization signals, respectively.

10. A timing apparatus according to claim 2, wherein the first and second delay characteristics correspond to an absolute time after the first and second synchronization signals at which the first and second sensors capture data, respectively.

11. A timing apparatus according to claim 6, wherein the first and second delay characteristics correspond to an absolute time after the first and second synchronization signals at which the first and second sensors capture data, respectively.

12. An apparatus for synchronizing timing metadata associated with sensor data, comprising:

a reliable time source that provides a periodic pulse; and

a synchronization circuit that provides synchronization signals to a plurality of sensors based on a common pre-trigger, the timing module accounting for respective delay characteristics of the sensors so that they all capture data at approximately the same absolute time in response to the synchronization signals, the synchronization circuit receiving the periodic pulse and determining a timing offset between the periodic pulse and the common pre-trigger.

13. An apparatus according to claim 12, wherein the reliable time source is a GPS receiver.

14. An apparatus according to claim 12, wherein the common pre-trigger has a rate corresponding to a desired frame rate of the sensor data.

15. An apparatus according to claim 12, further comprising a timing computer that receives the timing offset and certain of the synchronization signals and updates a frame counter corresponding to the captured data.

16. An apparatus according to claim 12, further comprising a timing computer that receives the timing offset from the synchronization circuit and absolute time information from the reliable time source, the timing computer making the timing offset and absolute time information available to external devices that use the captured data from the sensors so that the same absolute time can be determined and associated with the captured data from the sensors.

17. An apparatus according to claim 12, wherein the synchronization circuit includes:

a circuit for distributing a system clock;

a first synchronization counter that receives the system clock and the pre-trigger, the first synchronization counter generating a first one of the synchronization signals that is offset from the pre-trigger based on a first count of the system clock and a first one of the delay characteristics; and

a second synchronization counter that receives the system clock and the pre-trigger, the second synchronization counter generating a second one of the synchronization signals different from the first synchronization signal and that is offset from the pre-trigger based on a second count of the system clock and a second one of the delay characteristics.

18. An apparatus according to claim 17, wherein the first and second counts have a resolution of less than 50 nanoseconds.

19. An apparatus according to claim 17, further comprising a divider circuit that generates the pre-trigger based on a desired frame rate of the sensor data.

20. An apparatus according to claim 19, wherein the divider circuit generates the pre-trigger by dividing the system clock.

21. An apparatus according to claim 17, further comprising first and second pre-load registers for storing count values corresponding to the first and second delay characteristics, respectively, the first and second synchronization circuits using the count values to compare to the first and second counts of the system clock in determining when to generate the first and second synchronization signals, respectively.

22. An apparatus according to claim 21, further comprising a timing computer that receives the first and second delay characteristics and computes the count values for storing in the first and second pre-load registers.

23. A method of synchronizing timing metadata associated with sensor data, comprising:

receiving a periodic pulse from a reliable time source;

generating synchronization signals to a plurality of sensors based on a common pre-trigger, the synchronization signals being offset from the common pre-trigger in accordance with respective delay characteristics of the sensors so that they all capture data at approximately the same absolute time in response to the synchronization signals; and

determining a timing offset between the periodic pulse and the common pre-trigger.

24. A method according to claim 23, wherein the reliable time source is a GPS receiver.

25. A method according to claim 23, wherein the common pre-trigger has a rate corresponding to a desired frame rate of the sensor data.

26. A method according to claim 23, further comprising:

updating a frame counter corresponding to the captured data in accordance with the synchronization signals.

27. A method according to claim 23, further comprising:

receiving the timing offset;

receiving absolute time information from the reliable time source;

making the timing offset and absolute time information available to external devices that use the captured data from the sensors so that the same absolute time can be determined and associated with the captured data from the sensors.

28. A method according to claim 23, wherein the step of generating the synchronization signals includes:

receiving a system clock and the pre-trigger;

generating a first one of the synchronization signals that is offset from the pre-trigger based on a first count of the system clock and a first one of the delay characteristics; and

generating a second one of the synchronization signals different from the first synchronization signal and that is offset from the pre-trigger based on a second count of the system clock and a second one of the delay characteristics.

29. A method according to claim 28, wherein the first and second counts have a resolution of less than 50 nanoseconds.

30. A method according to claim 28, further comprising:

generating the pre-trigger by dividing the system clock.

31. A method according to claim 28, further comprising:

storing count values corresponding to the first and second delay characteristics,

using the count values to compare to the first and second counts of the system clock in determining when to generate the first and second synchronization signals, respectively.

32. A method according to claim 31, further comprising:

receiving information corresponding to the first and second delay characteristics; and

computing the count values for storing.