Multiple data bus synchronization

• US 7,334,065 B1
• Filed: 05/30/2002
• Issued: 02/19/2008
• Est. Priority Date: 05/30/2002
• Status: Expired due to Fees

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Batra, Jatin, Rose, Kenneth M.
• Primary Examiner(s): CHEN, ALAN S
• Application Number:
  US10/158,818
• Time in Patent Office: 2,091 Days
• Field of Search: 370/389, 370/392, 370/393, 710/26, 710/33, 710/52, 710/65
• US Class Current: 710/65
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: H04L 49/40 Constructional details, e.g. power supply, mechanical construction or backplane

Abstract

Disclosed is a method and circuit for synchronizing dual data buses. In one embodiment, the method includes a receiving circuit receiving first and second streams of multibit data portions transmitted via first and second parallel data buses, respectively, coupled thereto. The receiving circuit compares first-stream multibit data portions with a first predefined multibit data portion to identify a first-stream multibit data portion that matches the first predefined multibit data portion. The receiving circuit stores into a first FIFO, all first-stream multibit data portions that follow the identified first-stream multibit data portion. The receiving circuit also compares second-stream multibit data portions with a second predefined multibit data portion to identify a second-stream multibit data portion that matches the second predefined multibit data portion. The receiving circuit stores into a second FIFO, all second-stream multibit data portions that follow the identified second-stream multibit data portion.

Claims

1. A method comprising:

a receiving circuit receiving first and second streams of multibit data portions transmitted via first and second n-bit parallel data buses, respectively, coupled thereto;

the receiving circuit comparing first-stream multibit data portions with a first predefined multibit data portion to identify a first-stream multibit data portion that matches the first predefined multibit data portion;

the receiving circuit storing into a first FIFO buffer, all first-stream multibit data portions that follow the identified first-stream multibit data portion;

the receiving circuit comparing second-stream multibit data portions with a second predefined multibit data portion to identify a second-stream multibit data portion that matches the second predefined multibit data portion;

the receiving circuit storing into a second FIFO buffer, all second-stream multibit data portions that follow the identified second-stream multibit data portion;

concatenating second-stream multibit data portions stored in the second FIFO buffer with respective first-stream multibit data portions stored in the first FIFO buffer to form multibit data lines;

transmitting the multibit data lines via a 2n-bit parallel data bus.

2. The method of claim 1 wherein the first and second predefined multibit data portions are identical to each other.

3. The method of claim 1 further comprising:

the receiving circuit generating a first signal in response to identifying the first-stream multibit data portion that matches the first predefined multibit data portion;

the receiving circuit generating a second signal in response to identifying the second-stream multibit data portion that matches the second predefined multibit data portion;

the first FIFO buffer sequentially outputting each of the first-stream multibit data portions stored therein in response to the receiving circuit generating the first and second signals.

4. The method of claim 1 further comprising:

storing the multibit data lines in a data line FIFO buffer.

5. The method of claim 1 further comprising:

a transmitting circuit simultaneously transmitting first and second predefined multibit portions on the n-bit first and second parallel data buses, respectively, coupled thereto;

the transmitting circuit simultaneously transmitting first and second multibit data line portions on the n-bit first and second parallel data buses, respectively, after transmission of the first and second predefined multibit portions.

6. An apparatus comprising:

a n-bit first data bus;

a first memory circuit coupled to the first n-bit data bus, wherein the first memory circuit is configured to store first-stream multibit data portions transmitted over the first n-bit data bus;

a first circuit coupled to the first n-bit data bus and the first memory circuit, wherein the first circuit is configured to compare a first predefined multibit data portion with first-stream multibit data portions transmitted over the first n-bit data bus in order to identify a first-stream multibit data portion that matches the first predefined multibit data portion;

wherein first memory circuit is configured to store first-stream multibit data portions in response to the first circuit identifying the first-stream multibit data portion that matches the first predefined multibit data portion;

a second n-bit data bus;

a second memory circuit coupled to the second n-bit data bus, wherein the second memory circuit is configured to store second-stream multibit data portions transmitted over the second n-bit data bus;

a second circuit coupled to the second n-bit data bus and the second memory circuit, wherein the second circuit is configured to compare a second predefined multibit data portion with second-stream multibit data portions transmitted over the second n-bit data bus in order to identify a second-stream multibit data portion that matches the second predefined multibit data portion;

wherein second memory circuit is configured to store second-stream multibit data portions in response to the second circuit identifying the second-stream multibit data portion that matches the second predefined multibit data portion;

a circuit coupled to the first and second memory circuits, wherein the circuit is configured to concatenate respective multibit data portions stored in the first and second memory circuits to form multibit data lines;

a 2n-bit parallel data bus coupled to the circuit for transmitting the multibit data lines.

7. The apparatus of claim 6:

wherein the first memory circuit is configured to store only first-stream multibit data portions that sequentially follow the identified first-stream multibit data portion over the first n-bit data bus in response to the first circuit identifying the first-stream multibit data portion that matches the first predefined multibit data portion;

wherein the second memory circuit is configured to store only second-stream multibit data portions that sequentially follow the identified second-stream multibit data portion over the second n-bit data bus in response to the second circuit identifying the second-stream multibit data portion that matches the second predefined multibit data portion.

8. The apparatus of claim 7:

wherein the first memory circuit is configured to store only the identified first-stream data portion and first-stream multibit data portions that sequentially follow the identified first-stream multibit data portion over the first n-bit data bus in response to the first circuit identifying the first-stream multibit data portion that matches the first predefined multibit data portion;

wherein the second memory circuit is configured to store only the identified second-stream data portion and second-stream multibit data portions that sequentially follow the identified second-stream multibit data portion over the second n-bit data bus in response to the second circuit identifying the second-stream multibit data portion that matches the second predefined multibit data portion.

9. The apparatus of claim 6:

wherein the first memory circuit comprises a first FIFO buffer configured to store first-stream multibit data portions in response to the first circuit identifying the first-stream multibit data portion that matches the first predefined multibit data portion;

wherein the second memory circuit comprises a second FIFO buffer configured to store second-stream multibit data portions in response to the second circuit identifying the second-stream multibit data portion that matches the second predefined multibit data portion.

10. The apparatus of claim 6 wherein the first and second predefined multibit data portions are identical to each other.

11. The apparatus of claim 6 further comprising first and second transmitting circuits coupled to the first and second n-bit data buses, respectively, wherein the first and second transmitting circuits are configured to simultaneously transmit first and second predefined multibit data portions, respectively, on the first and second n-bit data buses, respectively, and wherein the first and second transmitting circuits are configured to simultaneously transmit first and second multibit data portions on the first and second n-bit data buses, respectively, after transmission of the first and second predefined multibit data portions.

12. A memory for storing instructions executable by a computer system, wherein computer system performs a method in response to executing the instructions, the method comprising:

comparing first-stream multibit data portions transmitted via a first n-bit parallel data bus with a first predefined multibit data portion to identify a first-stream multibit data portion that matches the first predefined multibit data portion;

storing into a first FIFO buffer, all first-stream multibit data portions that follow the identified first-stream multibit data portion;

comparing second-stream multibit data portions transmitted via a second n-bit parallel data bus with a second predefined multibit data portion to identify a second-stream multibit data portion that matches the second predefined multibit data portion;

storing into a second FIFO buffer, all second-stream multibit data portions that follow the identified second-stream multibit data portion;

concatenating second-stream multibit data portions stored in the second FIFO buffer with respective first-stream multibit data portions stored in the first FIFO buffer to form multibit data lines;

transmitting the multibit data lines onto a 2n-bit parallel data bus.

13. The memory of claim 12 wherein the method further comprises:

generating a first signal in response to identifying the first-stream multibit data portion that matches the first predefined multibit data portion;

generating a second signal in response to identifying the second-stream multibit data portion that matches the second predefined multibit data portion;

the first and second FIFO buffers outputting each of the first-stream multibit data portions and second-stream multibit data portions respectively stored therein in response to the generating the first and second signals.

14. The memory of claim 12 wherein the method further comprises:

storing the multibit data lines in a data line FIFO buffer.

15. The memory of claim 12 wherein the method further comprises:

simultaneously transmitting first and second predefined multibit portions over the first and second n-bit parallel data buses, respectively;

simultaneously transmitting first and second multibit data line portions on the first and second n-bit parallel data buses, respectively, after transmission of the first and second predefined multibit portions.

16. An apparatus comprising:

a first n-bit data bus;

a first memory circuit coupled to the first n-bit data bus, wherein the first memory circuit is configured to store first-stream multibit data portions transmitted sequentially over the first n-bit data bus;

a first means coupled to the first n-bit data bus and the first memory circuit, wherein the first means is configured to compare a first predefined multibit data portion with first-stream multibit data portions transmitted sequentially over the first n-bit data bus in order to identify a first-stream multibit data portion that matches the first predefined multibit data portion;

wherein first memory circuit is configured to store first-stream multibit data portions in response to the first means identifying the first-stream multibit data portion that matches the first predefined multibit data portion;

a second n-bit data bus;

a second memory circuit coupled to the second n-bit data bus, wherein the second memory circuit is configured to store second-stream multibit data portions transmitted sequentially over the second n-bit data bus;

a second means coupled to the second n-bit data bus and the second memory circuit, wherein the second means is configured to compare a second predefined multibit data portion with second-stream multibit data portions transmitted sequentially over the second n-bit data bus in order to identify a second-stream multibit data portion that matches the second predefined multibit data portion;

wherein second memory circuit is configured to store second-stream multibit data portions in response to the second means identifying the second-stream multibit data portion that matches the second predefined multibit data portion;

means for concatenating second-stream multibit data portions stored in the second memory circuit with respective first-stream multibit data portions stored in the first memory circuit to form multibit data lines;

a 2n-bit parallel data bus coupled for transmitting the multibit data lines.

17. A method comprising:

receiving first and second streams of multibit data transmitted via first and second n-bit parallel data buses, respectively;

comparing portions of the first-stream of multibit data with a first predefined multibit data portion to identify a portion of the first-stream of multibit that matches the first predefined multibit data portion;

storing into a first FIFO buffer, all portions of the first-stream of multibit data that follow the identified portion of the first-stream of multibit data that matches the first predefined multibit data portion;

comparing portions of the second-stream of multibit data with a second predefined multibit data portion to identify a portion of the second-stream of multibit data that matches the second predefined multibit data portion;

storing into a second FIFO buffer, all portions of the second-stream of multibit data that follow the identified portion of the second-stream of multibit data that matches the second predefined multibit data portion;

concatenating portions of the second-stream of multibit data stored in the second FIFO buffer with respective portions of the first-stream of multibit data stored in the first FIFO buffer to form multibit data lines;

transmitting the multibit data lines onto a 2n-bit parallel data bus.

18. The method of claim 17 further comprising an act of transmitting the multibit data lines to a switching fabric.