Method and system for multi-channel transfer of data and control

• US 7,334,074 B2
• Filed: 09/08/2006
• Issued: 02/19/2008
• Est. Priority Date: 05/03/2000
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rajan, Sundar
• Primary Examiner(s): Rinehart; Mark H.
• Assistant Examiner(s): Cerullo; Jeremy S
• Application Number:
  US11/518,122
• Publication Number:
  US 20070016713A1
• Time in Patent Office: 529 Days
• Field of Search: 710/306, 710/310, 710/311, 710/315
• US Class Current: 710/315
• CPC Class Codes: G06F 13/128 for dedicated transfers to a network for protocol converters G06F13/387
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 69/14 Multichannel or multilink protocols
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A system and method for transferring information in a multi-channel, point-to-point environment are described. In one embodiment, a number of processing chips are connected to a bridge bus. A bridge is connected to the bridge bus and to a system bus. In addition, a memory is connected to the bridge.

Claims

1. A system for transferring data in a multi-channel, point-to-point environment, the system comprising:

a plurality of processing chips connected to a bridge bus, the bridge bus having a first clock speed at which it operates;

a bridge having a second clock speed at which the bridge operates, the second clock speed being different from the first clock speed, wherein the bridge is connected to the bridge bus and to a system bus, the system bus having a third clock speed at which the system bus operates, the third clock speed being different from the first clock speed;

a plurality of buffers coupled to the bridge, wherein each buffer is assigned to a respective processing chip; and

a first memory connected to the bridge and having the ability to store cells that are exchanged between the bridge bus and the system bus, wherein each cell includes an address for at least one processing chip, wherein the bridge is has the ability to place a cell destined for a destination processing chip in a respective buffer assigned to the destination processing chip, and wherein the bridge is has the ability to place a cell received from an initiating processing chip in a location assigned to the initiating processing chip in a second memory coupled to the system bus.

2. The system of claim 1 wherein the bridge comprises:

a system bus interface connected to the system bus;

a memory interface connected to the system bus interface;

a cell initiated serial interface connected to the memory interface and to the bridge bus; and

a control logic connected to the system bus interface, the memory interface, and the cell initiated serial interface.

3. The system of claim 2 wherein the system bus interface further comprises a first-in first-out (FIFO) stack for storing write-postings of data cells.

4. The system of claim 2 wherein the cell initiated serial interface has the ability to generate null cells for transfer to the bridge bus.

5. The system of claim 2 wherein the cell initiated serial interface has the ability to remove null cells received from the bridge bus.

6. The system of claim 1 wherein the second clock speed is greater than the first clock speed.

7. The system of claim 1 wherein the second clock speed is greater than the third clock speed.

8. The system of claim 1 wherein the bridge bus has the ability to transfer data using a first data transfer protocol, wherein the system bus is adapted to transfer data using a second data transfer protocol, and wherein the first data transfer protocol and the second data transfer protocol are different data transfer protocols.

9. A bridge for transferring data in a multi-channel, point-to-point environment, wherein the bridge has a first clock speed at which it operates, the bridge comprising:

a system bus interface connected to a system bus, wherein the system bus has a second clock speed at which it operates, the second clock speed being different from the first clock speed;

a memory interface connected to the system bus interface and to a memory, wherein the memory has the ability to store cells that are transmitted over the point-to-point environment, each cell including an address for the at least one processing chip;

a cell initiated serial interface connected to the memory interface and to a bridge bus wherein the bridge bus has a third clock speed at which it operates, the third clock speed being different from the first clock speed; and

a control logic connected to the system bus interface, the memory interface, and the cell initiated serial interface, wherein the control logic has the ability to place a cell destined for a destination processing chip in a respective buffer assigned to a destination processing chip, and to place a cell received from an initiating processing chip in a second respective buffer assigned to the initiating processing chip.

10. The bridge of claim 9 wherein the system bus interface further comprises a first-in first-out (FIFO) stack for storing write-postings of data cells.

11. The bridge of claim 9 wherein the cell initiated serial interface has the ability to generate null cells for transfer to the bridge bus.

12. The bridge of claim 9 wherein the cell initiated serial interface has the ability to remove null cells received from the bridge bus.

13. The bridge of claim 9 wherein the first clock speed is greater than the second clock speed.

14. The bridge of claim 9 wherein the first clock speed is greater than the third clock speed.

15. The bridge of claim 9, wherein the bridge bus has a first data transfer protocol and the system bus has a second data transfer protocol, and wherein the first data transfer protocol and the second data transfer protocol are different data transfer protocols.