System and method for fabricating logic devices comprising carbon nanotube transistors

• US 7,335,603 B2
• Filed: 02/07/2001
• Issued: 02/26/2008
• Est. Priority Date: 02/07/2000
• Status: Expired due to Fees

• Current Assignee: Xidex Corp. (Anacomp Incorporated)
• Original Assignee: Xidex Corp. (Anacomp Incorporated)
• Inventors: Mancevski, Vladimir
• Primary Examiner(s): SMITH, BRADLEY
• Application Number:
  US09/779,374
• Publication Number:
  US 20010023986A1
• Time in Patent Office: 2,575 Days
• Field of Search: 438/758, 977/742, 257/E51.04
• US Class Current: 438/758
• CPC Class Codes: G01Q 70/12 Nanotube tips
• CPC Class Codes: H10K 10/46 Field-effect transistors, e.g. organic thin-film transistors [OTFT] H10K10/43 takes precedence
• CPC Class Codes: H10K 10/491 Vertical transistors, e.g. vertical carbon nanotube field effect transistors [CNT-FETs]
• CPC Class Codes: H10K 85/221 Carbon nanotubes
• CPC Class Codes: Y10S 977/742 Carbon nanotubes, CNTs

Abstract

Carbon nanotube devices and methods for fabricating these devices, wherein in one embodiment, the fabrication process consists of the following process steps: (1) generation of a template, (2) catalyst deposition, and (3) nanotube synthesis within the template. In another embodiment, a carbon nanotube transistor comprises a carbon nanotube having two or more defects, wherein the defects divide the carbon nanotube into three regions having differing conductivities. The defects may be introduced by varying the diameter of a template in which the carbon nanotube is fabricated and thereby causing pentagon-heptagon pairs which form the defects.

Claims

1. A device comprising:

a horizontally oriented substrate having;

a silicon layer containing at least one nano-sized diameter silicon pore,

a patterned conductive layer,

wherein at least one carbon nanotube is fabricated within the silicon pore,

wherein the at least one carbon nanotube is electrically coupled to the patterned conductive layer; and

wherein substantially all of the carbon nanotubes are vertically oriented.

2. The device of claim 1, wherein the at least one vertically oriented carbon nanotube is partially embedded within the silicon pore.

3. The device of claim 1, wherein the at least one vertically oriented carbon nanotube is fully embedded within the silicon pore without protruding beyond the silicon pore.

4. The device of claim 1, wherein the at least one vertically oriented carbon nanotubes is disposed outwardly from the silicon pore.

5. The device of claim 1, wherein the silicon layer comprises a material from a class consisting of undoped silicon, doped silicon, crystalline silicon, polysilicon, silicon nitride, undoped silicon dioxide, and doped silicon dioxide.

6. The device of claim 1, wherein at least one vertically oriented carbon nanotube is electrically isolated from the silicon layer.

7. The device of claim 1, wherein the at least one vertically oriented nanotube is fabricated within a specified area of the silicon layer.

8. A device of claim 1, comprising a second patterned conductive layer within the substrate.

9. A device of claim 1, wherein the pore diameter is preferably in the range from about 1 nanometer to about 50 nanometers.

10. The device of claim 1, wherein the carbon nanotube is conductive.

11. A device of claim 1, wherein the conductive layer material comprises a member of the class consisting of aluminum, copper, tungsten, titanium, nickel, chromium, and their alloys.