Structures of and methods of fabricating trench-gated MIS devices

• US 7,335,946 B1
• Filed: 07/22/2004
• Issued: 02/26/2008
• Est. Priority Date: 03/22/2002
• Status: Expired due to Term

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Bhalla, Anup, Lui, Sik, Pitzer, Dorman, Korec, Jacek, Shi, Xiaorong
• Primary Examiner(s): Parker; Kenneth
• Assistant Examiner(s): DIAZ, JOSE R
• Application Number:
  US10/898,431
• Time in Patent Office: 1,314 Days
• Field of Search: 257/334
• US Class Current: 257/334
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 257/905 Plural dram cells share common contact or common trench

Abstract

In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.

Claims

1. A trench-gated MIS device formed in a semiconductor chip and comprising:

a first active area and a second active area each comprising transistor cells;

a gate metal area containing no transistor cells; and

a gate metal layer,

wherein a plurality of trenches are formed in a pattern on a surface of the semiconductor chip, each trench extending from the first active area to the second active area and passing through the gate metal area, each trench having walls lined with a layer of an insulating material, a conductive gate material being disposed in each trench, a top surface of the conductive gate material being at a level below a top surface of the semiconductor chip, a nonconductive layer overlying the active and gate metal areas, a plurality of apertures being formed in the nonconductive layer, each aperture being formed over a portion of a respective trench in the gate metal area such that each aperture is spaced apart from each other, each aperture being filled with the gate metal layer such that the gate metal layer contacts the conductive gate material in an area of contact within each trench.

2. The trench-gated MIS device of claim 1 wherein said gate metal layer overlies the nonconductive layer in the gate metal area, the gate metal layer being in electrical contact with the conductive gate material.

3. The trench-gated MIS device of claim 2 wherein the gate metal layer extends longitudinally in a direction perpendicular to a direction of each trench in the gate metal area.

4. The trench-gated MIS device of claim 1 wherein a width of each trench at the area of contact between the gate metal layer and the conductive gate material is greater than a width of each trench in the first and second active areas.