Heterogeneously integrated microsystem-on-a-chip
First Claim
Patent Images
1. A microsystem-on-a-chip, comprising:
- a bottom chip comprising one or more microsystem devices with associated input/output pads on the top surface of the bottom chip;
an interconnect layer on the top surface of the bottom chip, the interconnect layer comprising a compliant dielectric material and an interconnect structure embedded in the compliant dielectric material, the interconnect structure comprising one or more via capture pads connected to the associated input/output pads on the top surface of the bottom chip; and
a thin upper chip on the interconnect layer, the thin upper chip comprising one or more microsystem devices with associated input/output pads on the top surface of the thin upper chip that are connected to the one or more via capture pads in the interconnect layer by conductive vias through the thin upper chip.
4 Assignments
0 Petitions
Accused Products
Abstract
A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated, ultra-miniaturized, higher performing, robust and cost-effective microsystem package. The highly integrated microsystem package, comprising electronics, sensors, optics, and MEMS, can be miniaturized both in volume and footprint to the size of a bottle-cap or less.
-
Citations
12 Claims
-
1. A microsystem-on-a-chip, comprising:
-
a bottom chip comprising one or more microsystem devices with associated input/output pads on the top surface of the bottom chip; an interconnect layer on the top surface of the bottom chip, the interconnect layer comprising a compliant dielectric material and an interconnect structure embedded in the compliant dielectric material, the interconnect structure comprising one or more via capture pads connected to the associated input/output pads on the top surface of the bottom chip; and a thin upper chip on the interconnect layer, the thin upper chip comprising one or more microsystem devices with associated input/output pads on the top surface of the thin upper chip that are connected to the one or more via capture pads in the interconnect layer by conductive vias through the thin upper chip. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
-
Specification