Wafer level chip scale package

• US 7,335,986 B1
• Filed: 09/14/2005
• Issued: 02/26/2008
• Est. Priority Date: 09/14/2005
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Jang, Ho Cheol, Jin, Jung Gi, Park, Sung Su, Paek, Jong Sik
• Primary Examiner(s): Le; Thao P.
• Application Number:
  US11/227,410
• Time in Patent Office: 895 Days
• Field of Search: 257/724, 257/725, 257/723, 257/737, 257/738, 257/759, 257/762, 257/777, 257/778
• US Class Current: 257/723
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48145 : the bodies being stacked
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 : the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/85 : using a wire connector
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/50 : for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/647 : Resistive arrangements H01L23/66, H01L23/62 take precedence
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19015 : including thin film passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip

Abstract

Disclosed is a wafer level chip scale package and a method for manufacturing the same. The wafer level chip scale package includes a semiconductor die having a first coating layer formed thereon; a redistribution layer formed on the first coating layer and connected to the bond pad; an electronic device placed on the first coating layer; a connection member for electrically connecting the electronic device and the redistribution layer; a conductive post formed on the redistribution layer with a predetermined thickness; a second coating layer for enclosing the first coating layer, the redistribution layer, the electronic device, the connection member, and the conductive post; and a solder ball thermally bonded to the conductive post while protruding to the exterior of the second coating layer. This construction makes it easy to manufacture stacked packages and chip scale packages in a wafer level.

Claims

1. A wafer level chip scale package comprising:

a semiconductor die comprising a first surface comprising at least one bond pad formed thereon and a first coating layer formed on the outer peripheral edge of the bond pad, a second surface opposing the first surface, and a third surface positioned along the periphery of the first and second surfaces;

a first redistribution layer along a surface of the first coating layer and being connected to the bond pad;

a first electronic device positioned on the surface of the first coating layer and connected to the first redistribution layer by a first connection member;

a first conductive post formed on the first redistribution layer; and

a second coating layer formed on the surface of the first coating layer, the first redistribution layer, the first electronic device, the first connection member, and the first conductive post in such a manner that a surface of the first conductive post is exposed to the exterior.

2. The wafer level chip scale package as claimed in claim 1, wherein the first coating layer is made of a photosensitive material.

3. The wafer level chip scale package as claimed in claim 1, wherein the first coating layer is made of any one chosen from a group consisting of BCB (benzocyclobutene) and PI (polyimide).

4. The wafer level chip scale package as claimed in claim 1, wherein the first connection member is any one chosen from a group consisting of a conductive wire and a conductive bump.

5. The wafer level chip scale package as claimed in claim 1, wherein the first conductive post is made of copper.

6. The wafer level chip scale package as claimed in claim 1, wherein the second coating layer is made of any one chosen from a group consisting of benzocyclobutene, polyimide, mold compound, and epoxy resin.

7. The wafer level chip scale package as claimed in claim 1, wherein the second and third surfaces of the semiconductor die are exposed to the exterior.

8. The wafer level chip scale package as claimed in claim 1, wherein the first electronic device is bonded to the surface of the first coating layer with an adhesive and the first connection member comprises a conductive wire.

9. The wafer level chip scale package as claimed in claim 1, wherein the first electronic device is any one chosen from a group consisting of a resistor, a capacitor, and an inductor and is formed on a surface of the second coating layer using a conductive film and being connected to the first redistribution layer.

10. The wafer level chip scale package as claimed in claim 9, wherein a third coating layer is formed on the surface of the second coating layer to cover the first electronic device.

11. The wafer level chip scale package as claimed in claim 1, wherein the first conductive post has a solder ball thermally bonded thereto.

12. The wafer level chip scale package as claimed in claim 1, wherein the first and second coating layers have a lateral surface which is flush with the third surface of the semiconductor die.

13. The wafer level chip scale package as claimed in claim 1, further comprising:

a second redistribution layer on a surface of the second coating layer and being connected to the first conductive post;

a second conductive post connected to the second redistribution layer; and

a third coating layer formed on the surface of the second coating layer, the second redistribution layer, and the second conductive post in such a manner that a surface of the second conductive post is exposed to the exterior.

14. The wafer level chip scale package as claimed in claim 13, wherein the third coating layer is made of any one chosen from a group consisting of benzocyclobutene, polyimide, mold compound, and epoxy resin.

15. The wafer level chip scale package as claimed in claim 13, wherein the second conductive post has a solder ball thermally bonded thereto.

16. The wafer level chip scale package as claimed in claim 13, wherein a second electronic device is positioned on the surface of the second coating layer and is connected to the second redistribution layer by a second connection member.

17. The wafer level chip scale package as claimed in claim 13, wherein the first, second, and third coating layers have a lateral surface which is flush with the third surface of the semiconductor die.

18. A wafer level chip scale package comprising:

a semiconductor die comprising a first surface comprising at least one bond pad formed thereon and a first coating layer formed on the outer peripheral edge of the bond pad, a second surface opposing the first surface, and a third surface positioned along the periphery of the first and second surfaces;

a first redistribution layer along a surface of the first coating layer and being connected to the bond pad;

a second coating layer formed on the surface of the first coating layer and the first redistribution layer;

a first electronic device positioned on a surface of the second coating layer and connected to the first redistribution layer by a first connection member;

a first conductive post formed on the first redistribution layer;

a third coating layer formed on the surface of the second coating layer, the first electronic device, and the first conductive post in such a manner that a surface of the first conductive post is exposed to the exterior;

a second redistribution layer on a surface of the third coating layer and contacting the first conductive post;

a second electronic device connected to the second redistribution layer by a second connection member;

a second conductive post formed on the second redistribution layer; and

a fourth coating layer formed on the surface of the third coating layer, the second redistribution layer, the second electronic device, the second connection member, and the second conductive post in such a manner that a surface of the second conductive post is exposed to the exterior.

19. The wafer level chip scale package as claimed in claim 18, wherein the second conductive post has a solder ball thermally bonded thereto.

20. A wafer level chip scale package comprising:

a semiconductor die comprising a first surface comprising bond pads formed thereon and a first coating layer formed on the outer peripheral edges of the bond pads, a second surface opposing the first surface, and a third surface positioned along the periphery of the first and second surfaces;

a first redistribution layer along a surface of the first coating layer and being connected to the bond pads;

a first electronic device positioned on the surface of the first coating layer and connected to the first redistribution layer by conductive wires;

conductive posts formed on the first redistribution layer;

a second coating layer formed on the surface of the first coating layer, the first redistribution layer, the first electronic device, the conductive wires, and the conductive posts in such a manner that surfaces of the conductive posts are exposed to the exterior, wherein the first and second coating layers have a lateral surface which is flush with the third surface of the semiconductor die; and

solder balls thermally bonded to the conductive posts.