Semiconductor component having multiple stacked dice

• US 7,335,994 B2
• Filed: 06/27/2005
• Issued: 02/26/2008
• Est. Priority Date: 01/27/2003
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Doan, Trung Tri, Wood, Alan G., Klein, Dean A.
• Primary Examiner(s): v Pham; Hoai
• Assistant Examiner(s): NGUYEN, DILINH P
• Application Number:
  US11/167,031
• Publication Number:
  US 20050242422A1
• Time in Patent Office: 974 Days
• Field of Search: 257685-686, 257/723, 257/777, 257/778, 257786-787, 257/790, 257/773, 257/730, 257/788, 257/731, 257/733, 257/E25.006, 257/E25.013, 257/E25.018, 257/E25.021, 257/E25.027, 257/E23.085, 257/E21.614, 257/E25.031, 257/E25.032, 257/E23.042, 361/735, 361/790, 361/792
• US Class Current: 257/778
• CPC Class Codes: B33Y 80/00 Products made by additive manufacturing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/1703 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/17051 Bump connectors having different shapes
• CPC Class Codes: H01L 2224/171 Disposition
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/06596 : Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/48 : Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A semiconductor package component includes a base die and a secondary die flip chip mounted to the base die. The base die includes a set of stacking contacts for flip chip mounting the secondary die to the base die, and a set of interconnect contacts configured as an internal signal transmission system, and a physical structure for supporting a terminal contact system of the package component. The package component also includes an encapsulant on the base die encapsulating the interconnect contacts, an underfill layer between the dice, and terminal contacts configured for flip chip mounting the package component to a supporting substrate. A method for fabricating the package component includes the steps of providing a base wafer containing a plurality of base dice, and flip chip mounting the secondary dice to the base dice on the base wafer. In addition the method includes the steps of forming and planarizing the interconnect contacts on the base dice, and forming the terminal contacts on the planarized interconnect contacts.

Claims

1. A semiconductor component comprising:

a base die comprising a plurality of integrated circuits and a plurality of bumped interconnect contacts configured as a signal transmission system for the component;

a thinned secondary die flip chip bonded to the base die in electrical communication with the bumped interconnect contacts;

a thinned second secondary die having a backside, the second secondary die flip chip bonded to the secondary die in electrical communication with the bumped interconnect contacts;

a plurality of conductors on the backside of the second secondary die in electrical communication with the bumped interconnect contacts having a plurality of pads in an area array;

a plurality of terminal contacts for the component on the pads; and

at least one encapsulant on the base die encapsulating the bumped interconnect contacts and at least partially encapsulating the secondary die and the second secondary die, with the backside of the second secondary die and an outside surface of the encapsulant forming a planar surface for the conductors.

2. The semiconductor component of claim 1 wherein the encapsulant comprises a first encapsulant encapsulating the bumped interconnect contacts and a second encapsulant forming the planar surface.

3. The semiconductor component of claim 1 wherein the base die comprises an application specific device and the secondary die and the second secondary die comprise memory devices.

4. A semiconductor component comprising:

a base die comprising a plurality of integrated circuits, a plurality of contacts in electrical communication with the integrated circuits, and a plurality of bumped interconnect contacts in electrical communication with the contacts;

a thinned first secondary die stacked on the base die comprising a circuit side, a plurality of bumped contacts on the circuit side bonded to the contacts on the base die, a back side and a plurality of contact pads on the back side in electrical communication with the bumped contacts;

a first encapsulant on the base die at least partially encapsulating the bumped interconnect contacts;

a thinned second secondary die flip chip bonded to the contact pads;

a second encapsulant on the first encapsulant having an outside surface which with a backside of the second secondary die forms a planar surface;

a plurality of second bumped interconnect contacts in the second encapsulant in electrical contact with the bumped interconnect contacts;

a plurality of conductors on the planar surface in electrical communication with the second bumped interconnect contacts having a plurality of terminal contact pads in an area array; and

a plurality of terminal contacts for the component on the terminal contact pads.

5. The semiconductor component of claim 4 wherein the first encapsulant and the second encapsulant comprise a curable polymer.

6. The semiconductor component of claim 4 wherein the first encapsulant and the second encapsulant comprise a laser imageable polymer.

7. The semiconductor component of claim 4 wherein the first encapsulant and the second encapsulant comprise a photo imageable polymer.

8. A system comprising:

a substrate comprising a plurality of electrodes; and

a semiconductor component on the substrate comprising;

a base die comprising a plurality of integrated circuits, a plurality contacts in electrical communication with the integrated circuits, and a plurality of interconnect contacts in electrical communication with the contacts;

a secondary die stacked on the base die in electrical communication with the base die and a second secondary die stacked on the secondary die in electrical communication with the secondary die;

a plurality of conductors on a back side of the second secondary die;

at least one encapsulant on the base die encapsulating the interconnect contacts and at least partially encapsulating the secondary die and the second secondary die, with the backside of the second secondary die and an outside surface of the encapsulant forming a planar surface for the conductors; and

a plurality of terminal contacts on the conductors bonded to the electrodes.

9. The system of claim 8 wherein the secondary die comprises a thinned die.

10. The system of claim 8 wherein the encapsulant comprises a first encapsulant encapsulating the interconnect contacts and a second encapsulant forming the planar surface.

11. The system of claim 8 wherein the base die has a first peripheral outline, the secondary die has a second peripheral outline, and the interconnect contacts are in an area between the first peripheral outline and the second peripheral outline.

12. The system of claim 8 wherein the terminal contacts comprise balls in a ball grid array or a fine ball grid array.

13. The system of claim 8 wherein the system comprises a multi chip module.

14. The system of claim 8 wherein the system comprises a system in a package.

15. The system of claim 8 wherein the system comprises a computer.