Non-volatile memory device and drive method thereof

• US 7,336,534 B2
• Filed: 12/30/2004
• Issued: 02/26/2008
• Est. Priority Date: 12/31/2003
• Status: Active Grant

• Current Assignee: DB HiTek Co., Ltd.
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Jung, Jin Hyo
• Primary Examiner(s): Nguyen, Van Thu
• Assistant Examiner(s): Sofocleous, Alexander
• Application Number:
  US11/024,468
• Publication Number:
  US 20050141272A1
• Time in Patent Office: 1,153 Days
• Field of Search: 365/154, 365/185.01, 365/185.07, 365/185.08, 365/185.26
• US Class Current: 365/185.08
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence

Abstract

A non-volatile memory device and drive method thereof uses a voltage bias condition to enable an electronic device to normally operate without employing a specific transistor, e.g., a recall transistor. The non-volatile memory device performs its function normally without the recall transistor, and by which a degree of cell integration can be considerably raised. A SRAM latch is controlled by the logic circuit, a SONOS (silicon-oxide-nitride-oxide-silicon) transistor is electrically connected to a Vcc node of the electronic device to store a high/low state of the SRAM latch according to a turn-on or turn-off state of power, and a pass transistor controls read, program, and erase operations of the SONOS transistor.

Claims

1. A non-volatile memory device, which is provided within an electronic device having a logic circuit, the non-volatile memory device comprising:

a SRAM latch contained in a memory cell controlled by the logic circuit;

a SONOS, silicon-oxide-nitride-oxide-silicon, transistor disposed within the memory cell and electrically connected via a first terminal directly to a Vcc node of the electronic device, without a recall transistor connected therebetween, and configured to store a high/low state of the SRAM latch according to a turn-on or turn-off state of power of the electronic device;

a pass transistor disposed in the memory cell between the SRAM latch and the SONOS transistor and configured to control read, program, and erase operations of the SONOS transistor, wherein a first pass transistor terminal connected to a second SONOS terminal, and a second pass transistor terminal connected to said SRAM latch; and

a switch mechanism configured to controllably place said Vcc node in and out of a floating state depending on the operation being performed by said pass transistor.

2. The device of claim 1, wherein, the switch mechanism includes a transistor and a control circuit, said control circuit configured to controllably set said transistor in a non-conducting state when setting the Vcc node in the memory cell in the floating state.

3. A method of driving a non-volatile memory device, which is provided within an electronic device having a logic circuit and includes a SRAM latch controlled by the logic circuit, a SONOS transistor electrically connected via a first terminal directly to a Vcc node of the electronic device without a transistor connected therebetween and configured to store a high/low state of the SRAM latch according to a turn-on or turn-off state of power of the electronic device, a pass transistor disposed between the SRAM latch and the SONOS configured to control read, program, and erase operations of the SONOS transistor, and a switch mechanism configured to controllably place a Vcc node in and out of a floating state depending on the operation being performed by said pass transistor, the method comprising the steps of:

erasing a stored charge in the transistor including

applying a negative voltage to the SONOS transistor and a first voltage to the pass transistor, and setting the Vcc node to a floating state when the electronic device is set in the turn-off state, and

selectively storing the high/low state stored in the SRAM latch by applying a positive voltage to the SONOS transistor, a positive voltage to the pass transistor, and setting the Vcc node to the floating state.

4. The method of claim 3, further comprising the step of:

if the electronic device is in the turn-on state, isolating the SONOS transistor from the SRAM latch by applying the first voltage to the transistor and the pass transistor, and by floating the Vcc node.

5. The method of claim 3, further comprising the steps of if the electronic device is in the turn-off state, recalling information stored in the SONOS transistor to the SRAM latch by applying the positive voltage to the Vcc node, the first voltage to the SONOS transistor, and the positive voltage to the pass transistor.

6. The method of claim 3, wherein the first voltage is a ground voltage.

7. The method of claim 4, wherein the first voltage is a ground voltage.

8. The method of claim 5, wherein the first voltage is a ground voltage.