Non-volatile memory device and drive method thereof
First Claim
1. A non-volatile memory device, which is provided within an electronic device having a logic circuit, the non-volatile memory device comprising:
- a SRAM latch contained in a memory cell controlled by the logic circuit;
a SONOS, silicon-oxide-nitride-oxide-silicon, transistor disposed within the memory cell and electrically connected via a first terminal directly to a Vcc node of the electronic device, without a recall transistor connected therebetween, and configured to store a high/low state of the SRAM latch according to a turn-on or turn-off state of power of the electronic device;
a pass transistor disposed in the memory cell between the SRAM latch and the SONOS transistor and configured to control read, program, and erase operations of the SONOS transistor, wherein a first pass transistor terminal connected to a second SONOS terminal, and a second pass transistor terminal connected to said SRAM latch; and
a switch mechanism configured to controllably place said Vcc node in and out of a floating state depending on the operation being performed by said pass transistor.
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Accused Products
Abstract
A non-volatile memory device and drive method thereof uses a voltage bias condition to enable an electronic device to normally operate without employing a specific transistor, e.g., a recall transistor. The non-volatile memory device performs its function normally without the recall transistor, and by which a degree of cell integration can be considerably raised. A SRAM latch is controlled by the logic circuit, a SONOS (silicon-oxide-nitride-oxide-silicon) transistor is electrically connected to a Vcc node of the electronic device to store a high/low state of the SRAM latch according to a turn-on or turn-off state of power, and a pass transistor controls read, program, and erase operations of the SONOS transistor.
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Citations
8 Claims
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1. A non-volatile memory device, which is provided within an electronic device having a logic circuit, the non-volatile memory device comprising:
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a SRAM latch contained in a memory cell controlled by the logic circuit; a SONOS, silicon-oxide-nitride-oxide-silicon, transistor disposed within the memory cell and electrically connected via a first terminal directly to a Vcc node of the electronic device, without a recall transistor connected therebetween, and configured to store a high/low state of the SRAM latch according to a turn-on or turn-off state of power of the electronic device; a pass transistor disposed in the memory cell between the SRAM latch and the SONOS transistor and configured to control read, program, and erase operations of the SONOS transistor, wherein a first pass transistor terminal connected to a second SONOS terminal, and a second pass transistor terminal connected to said SRAM latch; and a switch mechanism configured to controllably place said Vcc node in and out of a floating state depending on the operation being performed by said pass transistor. - View Dependent Claims (2)
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3. A method of driving a non-volatile memory device, which is provided within an electronic device having a logic circuit and includes a SRAM latch controlled by the logic circuit, a SONOS transistor electrically connected via a first terminal directly to a Vcc node of the electronic device without a transistor connected therebetween and configured to store a high/low state of the SRAM latch according to a turn-on or turn-off state of power of the electronic device, a pass transistor disposed between the SRAM latch and the SONOS configured to control read, program, and erase operations of the SONOS transistor, and a switch mechanism configured to controllably place a Vcc node in and out of a floating state depending on the operation being performed by said pass transistor, the method comprising the steps of:
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erasing a stored charge in the transistor including applying a negative voltage to the SONOS transistor and a first voltage to the pass transistor, and setting the Vcc node to a floating state when the electronic device is set in the turn-off state, and selectively storing the high/low state stored in the SRAM latch by applying a positive voltage to the SONOS transistor, a positive voltage to the pass transistor, and setting the Vcc node to the floating state. - View Dependent Claims (4, 5, 6, 7, 8)
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Specification