Use of radiation-hardened chalcogenide technology for spaceborne reconfigurable digital processing systems

• US 7,337,160 B2
• Filed: 08/12/2004
• Issued: 02/26/2008
• Est. Priority Date: 12/31/2002
• Status: Expired due to Term

• Current Assignee: Gula Consulting Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: BAE Systems Information and Electronic Systems Integration Incorporated (BAE Systems Plc)
• Inventors: Marshall, Joseph R., Berger, Richard W., Rodgers, John C.
• Primary Examiner(s): STARKS, WILBERT L
• Application Number:
  US10/918,814
• Publication Number:
  US 20050027409A1
• Time in Patent Office: 1,293 Days
• Field of Search: 706/62, 706/45, 365/163, 365/226, 348/148, 257/678
• US Class Current: 706/62
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: H10B 63/10 Phase change RAM [PCRAM, PRAM] devices

Abstract

Chalcogenide technology is used for radiation hardening for spaceborne systems and more particularly in C-RAM form for processors, field programmable gate arrays, startup RAMs, shadow storage and single-chip systems to protect these units.

Claims

1. A method for improving the non-volatility and radiation hardening of a spaceborne system involving reconfigurable components comprising the step of providing at least one of the reconfigurable components with reconfigurable chalcogenide-based switching components.

2. The method of claim 1 wherein the switching components are provided as part of a random access memory, thus to provide for radiation hardening thereof.

3. The method of claim 1, wherein the spaceborne system includes multi-processors and multi-processor architecture.

4. The method of claim 1, wherein the spaceborne system includes hardware building blocks utilizing the chalcogenide technology, the hardware building blocks taken from the group consisting of arrays of data latches, reprogrammable analog devices, multi-state memory, and field programmable gate arrays.

5. The method of claim 1, wherein one of the hardware building blocks includes a read-only memory.

6. The method of claim 1, wherein one of the bardware building blocks is embedded within a chip as a core and includes a field programmable gate array.

7. The method of claim 1, wherein one of the hardware building blocks includes a random access memory.

8. The method of claim 1, wherein one of the hardware building blocks includes a shadow state storage having a reversible chalcogenide fuse, wire or configuration bit.

9. The method of claim 1, wherein the spaceborne system includes software building blocks utilizing the chalcogenide technology and not including hardware building blocks involving programming circuits.

10. The method of claim 9, wherein at least one of the software building blocks includes a chalcogenide-based memory.

11. The method of claim 1, wherein the spaceborne system includes a reversible chalcogenide fuse, wire or configuration bit.

12. The method of claim 11, wherein the spaceborne system includes a switching element and wherein the fuse, wire or configuration bit is in series with the switching element.

13. A method for improving the non-volatility and radiation hardening a spaceborne system, comprising the step of providing the spaceborne system with reconfigurable elements employing chalcogenide-based switching elements.

14. A method for improving the non-volatility and radiation hardening a spaceborne system, comprising the step of providing the spaceborne system with a C-RAM-based ROM.

15. A method for improving the non-volatility and radiation hardening a spaceborne system, comprising the step of providing the system with a C-RAM-based FPGA element embedded within a chip as a core.

16. A method for improving the non-volatility and radiation hardening a spaceborne system, comprising the step of implementing the spaceborne system in a single chip that includes internal C-RAM devices having at least one switching component employing a reversible chalcogenide fuse, wire or configuration chip.

17. The method of claim 16, wherein the single chip includes at least one C-RAM.