I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures

• US 7,337,249 B2
• Filed: 06/20/2007
• Issued: 02/26/2008
• Est. Priority Date: 12/20/1996
• Status: Expired due to Fees

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Pact XPP Technologies, AG
• Inventors: Vorbach, Martin, Münch, Robert
• Primary Examiner(s): Ray; Gopal C.
• Application Number:
  US11/820,943
• Publication Number:
  US 20070255882A1
• Time in Patent Office: 251 Days
• Field of Search: 710/100, 710/300, 710/8, 710/72, 710/305, 712/11, 712/14, 712/18, 716/16, 716/17, 326/38, 326/39, 326/41, 439/68
• US Class Current: 710/100
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).

Claims

1. A method of controlling communication between a plurality of cells arranged in a multidimensional cell structure and at least one external cell, comprising:

for write access to the at least one external cell;

transmitting data of the plurality of cells on lines of an internal bus interconnecting the plurality of cells and to write registers assigned to the lines; and

switching the write registers to an external bus in communication with the at least one external cell via opening of respective gates; and

for read access from the at least one external cell;

transmitting data of the at least one external cell to read registers assigned to the lines; and

switching the read registers to the lines of the internal bus via opening of the gates;

wherein only one gate is open at a time.

2. The method of claim 1, further comprising:

for each of the read and write registers, indicating in a corresponding state register whether the state register'"'"'s corresponding register includes data to be one of written and read.

3. The method of claim 1, further comprising:

an address generator one of incrementing and decrementing a value after each read, the value being used to address the read registers.

4. The method of claim 3, wherein the value is one of incremented and decremented to a predetermined value, the method further comprising:

setting a bit to indicate termination of address generation responsive to the value being set to the predetermined value.