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Hierarchical, programmable-priority content addressable memory system

  • US 7,337,267 B1
  • Filed: 02/10/2004
  • Issued: 02/26/2008
  • Est. Priority Date: 02/10/2004
  • Status: Expired due to Fees
First Claim
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1. A content addressable memory (CAM) system comprising:

  • a first CAM device having a priority number output, a first enable input, a CAM core to output a local match address, and a cascade logic circuit to output the local match address from the first CAM device in response to assertion of a first enable signal at the first enable input;

    a second CAM device having a priority number input and an enable output coupled to the priority number output and the first enable input, respectively, of the first CAM device, the second CAM device further having a priority number output and an enable input; and

    a third CAM device having a priority number input and an enable output coupled to the priority number output and the enable input, respectively, of the second CAM device.

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