Free list and ring data structure management
First Claim
Patent Images
1. A method comprising:
- checking a content addressable memory for a tag corresponding to a queue of data buffers associated with a dequeue request;
accessing a queue descriptor, for the queue of data buffers, in a cache memory based on a result of the checking;
removing a data buffer from the queue of data buffers using the queue descriptor from the cache memory;
processing information in the removed data buffer; and
appending the data buffer to a queue of currently unused buffers in response to an enqueue request.
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Accused Products
Abstract
A method of managing a free list and ring data structure, which may be used to store journaling information, by storing and modifying information describing a structure of the free list or ring data structure in a cache memory that may also be used to store information describing a structure of a queue of buffers.
345 Citations
76 Claims
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1. A method comprising:
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checking a content addressable memory for a tag corresponding to a queue of data buffers associated with a dequeue request; accessing a queue descriptor, for the queue of data buffers, in a cache memory based on a result of the checking; removing a data buffer from the queue of data buffers using the queue descriptor from the cache memory; processing information in the removed data buffer; and appending the data buffer to a queue of currently unused buffers in response to an enqueue request. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method comprising:
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removing a currently unused buffer from a queue of currently unused buffers in response to a dequeue request; processing a newly received data packet; storing the newly received data packet in the removed buffer; checking a content addressable memory for a tag corresponding to a queue of data buffers associated with an enqueue request; accessing a queue descriptor, for the queue of data buffers, in a cache memory based on a result of the checking; appending the removed buffer to the queue of data buffers using the queue descriptor from the cache memory. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A method comprising:
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receiving a request to write data to a memory ring data structure; and issuing a command, in response to the request, the command specifying a pointer to a memory location in which the data is to be inserted, said pointer describing a structure of the memory ring; writing data to a memory ring address identified by the information describing a structure of the memory ring; incrementing a pointer to a memory location in which data is to be inserted, said pointer describing a structure of the memory ring; incrementing the number of entries in the ring, said number of entries describing a structure of the memory ring; and storing the modified pointer and number of entries which describe a structure of the memory ring in a cache memory having entries to store information describing a structure of a queue of data buffers or a structure of a queue of currently unused buffers. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21)
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22. A method comprising:
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receiving a request to read data from a memory ring data structure; and issuing a command, in response to the request, specifying a pointer to a memory location from which the data is to be removed, said pointer describing a structure of the memory ring; reading data from a memory ring address identified by the information describing a structure of the memory ring; incrementing a pointer to a memory location from which data is to be removed, said pointer describing a structure of the memory ring; decrementing the number of entries in the ring, said number of entries describing a structure of the memory ring; and storing the modified pointer and number of entries which describe a structure of the memory ring in a cache memory having entries to store information describing a structure of a queue of data buffers. - View Dependent Claims (23, 24)
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25. An apparatus comprising:
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a processor providing a queue manager and a content addressable memory to store tags associated with buffer queues; a first memory coupled to the processor to store a queue of data buffers and at least one of a queue of currently unused buffers or a ring data structure; a cache memory coupled to the processor to store information describing a structure of the queue of data buffers and information describing at least one of a structure of the queue of currently unused buffers or a structure of the memory ring; and a second memory to store instructions that, when applied to the processor, cause the processor to; check the content addressable memory for a tag corresponding to the queue of data buffers; access the information describing the structure of the queue of data buffers in the cache memory based on a result of the check; remove a data buffer from the queue of data buffers using the information from the cache memory describing the structure of the queue of data buffers; process information in the removed data butter; and append the data buffer to a queue of currently unused buffers in response to an enqueue request. - View Dependent Claims (26, 27, 28, 29)
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30. An apparatus comprising:
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a processor providing a queue manager and a content addressable memory to store tags associated with buffer queues; a first memory coupled to the processor to store a queue of data buffers and at least one of a queue of currently unused buffers or a ring data structure; a cache memory coupled to the processor to store information describing a structure of a queue of data buffers and information describing at least one of a structure of the queue of currently unused buffers or a structure of the memory ring; and a second memory to store instructions that, when applied to the processor, cause the processor to; remove a currently unused buffer from a queue of currently unused buffers in response to a dequeue request; process a newly received data packet; store the newly received data packet in the removed buffer; check the content addressable memory for a tag corresponding to the queue of data buffers; access the information describing the structure of the queue of data buffers in the cache memory based on a result of the check; and append the removed buffer to the queue of data buffers using the queue descriptor from the cache memory. - View Dependent Claims (31, 32, 33, 34)
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35. An apparatus comprising:
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a processor providing a queue manager; a first memory coupled to the processor to store a queue of data buffers and at least one of a queue of currently unused buffers or a ring data structure; a cache memory coupled to the processor to store information describing a structure of the queue of data buffers and information describing at least one of a structure of the queue of currently unused buffers or a structure of the memory ring; and a second memory to store instructions that, when applied to the processor, cause the processor to; receive a request to write data to a memory ring data structure; issue a command, in response to the request, the command specifying a pointer to a memory location where the data is to be inserted, said pointer describing a structure of the memory ring; write data to a memory ring address identified by the information describing a structure of the memory ring; increment a pointer to a memory location where data is to be inserted, said pointer describing a structure of the memory ring; increment the number of entries in the ring, said number of entries describing a structure of the memory ring; and store the modified pointer and number of entries which describe a structure of the memory ring in a cache memory having entries to store information describing a structure of a queue of data buffers or a structure of a queue of currently unused buffers. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43)
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44. An apparatus comprising:
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a processor providing a queue manager; a first memory coupled to the processor to store a queue of data buffers and at least one of a queue of currently unused buffers or a ring data structure; a cache memory coupled to the processor to store information describing a structure of the queue of data buffers and information describing at least one of a structure of the queue of currently unused buffers or a structure of the memory ring; and a second memory to store instructions that, when applied to the processor, cause the processor to; receive a request to read data from a memory ring data structure; and issue a command, in response to the request, specifying a pointer to a memory location from which the data is to be removed, said pointer describing a structure of the memory ring; read data from a memory ring address identified by the information describing a structure of the memory ring; increment a pointer to a memory location where data is to be removed, said pointer describing a structure of the memory ring; decrement the number of entries in the ring, said number of entries describing a structure of the memory ring; and store the modified pointer and number of entries which describe a structure of the memory ring in a cache memory having entries to store information describing a structure of a queue of data buffers. - View Dependent Claims (45, 46)
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47. A system comprising:
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a source of data packets; a destination of data packets; and a device operating to transfer data packets from the source to the destination comprising; a processor providing a queue manager; a first memory coupled to the processor to store a queue of data buffers and at least one of a queue of currently unused buffers or a ring data structure; a cache memory coupled to the processor to store information describing a structure of the queue of data buffers and information describing at least one of a structure of the queue of currently unused buffers or a structure of the memory ring; and a second memory to store instructions that, when applied to the processor, cause the processor to; remove a data buffer from a linked list of data buffers; process information in the removed data buffer; append the data buffer to a queue of currently unused buffers; store information describing a structure of a queue of currently unused buffers and a queue of data buffers; and modify information describing a structure of the queue of currently unused buffers. - View Dependent Claims (48, 49, 50)
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51. A system comprising:
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a source of data packets; a destination of data packets; and a device operating to transfer data packets from the source to the destination comprising; a processor providing a queue manager; a first memory coupled to the processor to store a queue of data buffers and at least one of a queue of currently unused buffers or a ring data structure; a cache memory coupled to the processor to store information describing a structure of a queue of data buffers and information describing at least one of a structure of the queue of currently unused buffers or a structure of the memory ring; and a second memory to store instructions that, when applied to the processor, cause the processor to; remove a currently unused buffer from a queue of currently unused buffers; process a newly received data packet; store the newly received data packet in the removed buffer; append the removed buffer to a linked list of data buffers; store information describing a structure of a queue of currently unused buffers and a queue of data buffers in a cache memory having entries to store information describing a structure of a queue of data buffers or a structure of a queue of currently unused buffers; and modify information describing a structure of the queue of currently unused buffers. - View Dependent Claims (52)
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53. An article comprising a storage medium having stored thereon instructions that, when executed by a machine, cause the machine to:
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check a content addressable memory for a tag corresponding to a queue of data buffers associated with a dequeue request; access a queue descriptor, for the queue of data buffers, in a cache memory based on a result of the check; remove a data buffer from the queue of data buffers using the queue descriptor from the cache memory process information in the removed data buffer; and append the data buffer to a queue of currently unused buffers in response to an enqueue request. - View Dependent Claims (54, 55, 56, 57, 58)
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59. An article comprising a storage medium having stored thereon instructions that, when executed by a machine, cause the machine to:
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remove a currently unused buffer from a queue of currently unused buffers in response to a dequeue request; process a newly received data packet; store the newly received data packet in the removed buffer; check a content addressable memory for a tag corresponding to a queue of data buffers associated with an enqueue request; access a queue descriptor, for the queue of data buffers, in a cache memory based on a result of the check; append the removed buffer to the queue of data buffers using the queue descriptor from the cache memory. - View Dependent Claims (60, 61, 62, 63, 64)
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65. An article comprising a storage medium having stored thereon instructions that, when executed by a machine, cause the machine to:
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receive a request to write data to a memory ring data structure; and issue a command, in response to the request, the command specifying a pointer to a memory location where the data is to be inserted, said pointer describing a structure of the memory ring; write data to a memory ring address identified by the information describing a structure of the memory ring; increment a pointer to a memory location where data is to be inserted, said pointer describing a structure of the memory ring; increment the number of entries in the ring, said number of entries describing a structure of the memory ring; and store the modified pointer and number of entries which describe a structure of the memory ring in a cache memory having entries to store information describing a structure of a queue of data buffers or a structure of a queue of currently unused buffers. - View Dependent Claims (66, 67, 68, 69, 70, 71, 72, 73)
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74. An article comprising a storage medium having stored thereon instructions that, when executed by a machine, cause the machine to:
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receive a request to read data from a memory ring data structure; and issue a command, in response to the request, specifying a pointer to a memory location where the data is to be removed, said pointer describing a structure of the memory ring; read data from a memory ring address identified by the information describing a structure of the memory ring; increment a pointer to a memory location where data is to be removed, said pointer describing a structure of the memory ring; decrement the number of entries in the ring, said number of entries describing a structure of the memory ring; and store the modified pointer and number of entries describing a structure of the memory ring in a cache memory having entries to store information describing a structure of a queue of data buffers. - View Dependent Claims (75, 76)
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Specification