Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device

• US 7,338,884 B2
• Filed: 11/29/2004
• Issued: 03/04/2008
• Est. Priority Date: 09/03/2001
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kikuchi, Katsumi, Matsui, Koji, Baba, Kazuhiro, Shimoto, Tadanori
• Primary Examiner(s): Lebentritt; Michael
• Assistant Examiner(s): Mitchell; James M
• Application Number:
  US10/997,986
• Publication Number:
  US 20050130413A1
• Time in Patent Office: 1,191 Days
• Field of Search: None
• US Class Current: 438/459
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H05K 1/112 directly combined with via connections
• CPC Class Codes: H05K 3/20 by affixing prefabricated conductor pattern H05K1/187, H05K3/046, H05K3/4658, H05K3/4682 takes precedence
• CPC Class Codes: H05K 3/4644 by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602

Abstract

An interconnecting substrate for carrying a semiconductor device, comprising: an insulating layer; an interconnection set on an obverse surface of the insulating layer; an electrode which is set on a reverse surface side of the insulating layer and formed in such a way that, at least, a lateral face of an obverse end of the electrode is all round brought into contact with the insulating layer, while, at least, a reverse surface of the electrode is not in contact with said insulating layer; a via conductor which is disposed on an obverse surface of the electrode and formed in the insulating layer so as to connect this electrode with the interconnection; and a supporting structure on the surface of the insulating layer.

Claims

1. A method of producing an interconnecting substrate for carrying a semiconductor device, comprising the steps of:

forming an electrode pattern on a substrate;

forming, on said substrate, an insulating layer so as to cover said electrode pattern;

forming, in said insulating layer, a via hole to reach said electrode pattern;

forming, on said insulating layer, a conductive substance layer so as to fill up said via hole, and then forming an interconnection pattern by patterning said conductive substance layer;

removing at least part of said substrate to expose an entire reverse side surface of said electrode pattern; and

forming a dielectric substance layer on a prescribed section of said electrode pattern, after forming said pattern,

wherein said dielectric substance layer, said electrode pattern lying under the dielectric substance layer and said conductive substance layer filling up the via hole made down to said dielectric substance layer constitute a capacitor.

2. A method of producing an interconnecting substrate for carrying a semiconductor device, comprising the steps of:

forming an electrode pattern on a substrate;

forming, on said substrate, an insulating layer so as to cover said electrode pattern;

forming, in said insulating layer, a via hole to reach said electrode pattern;

forming, on said insulating layer, a conductive substance layer so as to fill up said via hole, and then forming an interconnection pattern by patterning said conductive substance layer; and

removing at least part of said substrate to expose an entire reverse side surface of said electrode pattern,

wherein the removing step is carried out after loading a semiconductor device thereon.

3. A method of producing an interconnecting substrate for carrying a semiconductor device, comprising the steps of:

forming an electrode pattern on a substrate;

forming, on said substrate, an insulating layer so as to cover said electrode pattern;

forming, in said insulating layer, a via hole to reach said electrode pattern;

forming, on said insulating layer, a conductive substance layer so as to fill up said via hole, and then forming an interconnection pattern by patterning said conductive substance layer;

removing at least part of said substrate to expose an entire reverse side surface of said electrode pattern; and

removing a portion of said exposed electrode pattern by selective etching, as thick as prescribed, and thereby a sunken section is formed on a reverse surface of said insulating layer.

4. A method of producing an interconnecting substrate for carrying a semiconductor device, comprising the steps of:

forming an electrode pattern on a substrate;

forming, on said substrate, an insulating layer so as to cover said electrode pattern;

forming, in said insulating layer, a via hole to reach said electrode pattern;

forming, on said insulating layer, a conductive substance layer so as to fill up said via hole, and then forming an interconnection pattern by patterning said conductive substance layer; and

removing at least part of said substrate to expose an entire reverse side surface of said electrode pattern,

wherein, in the step of forming an electrode pattern on said substrate, with a conductive substrate being used as said substrate, a resist layer which has an opening pattern corresponding to the electrode pattern is formed on said substrate, and a deposition of metal is made inside of said opening pattern by the plating method, whereby said electrode pattern is formed.

5. A method of producing an interconnecting substrate for carrying a semiconductor device according to claim 4, wherein etching of said substrate is carried out, using said resist layer as a mask, and thereby a sunken section corresponding to said opening pattern of the resist layer is formed on an obverse surface of said substrate, and thereafter said electrode pattern is formed through a deposition of metal made on this sunken section.

6. A method of producing an interconnecting substrate for carrying a semiconductor device according to claim 4, wherein, in formation of said electrode pattern, there is formed a layered structure of said electrode pattern in which a Cu layer is disposed in an obverse end section and, at least, one layer of another conductive substance is disposed on a reverse end side thereof.

7. A method of producing an interconnecting substrate for carrying a semiconductor device according to claim 4, wherein, in formation of said electrode pattern, there is formed a layered structure of said electrode pattern in which a Cu layer is disposed in an obverse end section, a barrier conductive layer to prevent diffusion of solder is disposed on a reverse end side thereof, and a barrier conductive layer to etching removal of said substrate is disposed on a further reverse end side thereof.

8. A method of producing an interconnecting substrate for carrying a semiconductor device according to claim 4, wherein said substrate is a stainless steel board, and said electrode pattern is formed, on said substrate, by laying a Au plating layer, a Ni plating layer and a Cu plating layer in this order.

9. A method of producing an interconnecting substrate for carrying a semiconductor device according to claim 4, wherein said substrate is a Cu board or a Cu alloy board, and said electrode pattern is formed, on said substrate, by laying a Ni plating layer, a Au plating layer, a Ni plating layer and a Cu plating layer in this order.

10. A method of producing an interconnecting substrate for carrying a semiconductor device according to claim 4, wherein said electrode pattern is formed, on said substrate, by laying a Cu plating layer, a Ag plating layer and a Cu plating layer in this order.

11. A method of producing an interconnecting substrate for carrying a semiconductor device, comprising the steps of:

preparing a layered board wherein a first substrate and a second substrate are bonded together;

forming a first electrode pattern on said first substrate, and forming a second electrode pattern on said second substrate;

forming a first and a second insulting layer on said layered board so as to cover said first and said second electrode pattern, respectively;

forming, in said first insulating layer, a via hole to reach said first electrode pattern and forming, in said second insulating layer, a via hole to reach said second electrode pattern;

forming respective conductive substance layers on said first and said second insulating layer so as to fill up said via holes, and forming a first and a second interconnection pattern by patterning said respective conductive substance layers; and

separating said first substrate and said second substrate.

12. A method of producing an interconnecting substrate for carrying a semiconductor device according to claim 11, further comprising the step of applying selective removing onto each of said first and second substrates, after separating said first and said second substrates, and thereby, along with exposing said electrode patterns, making supporting structures of the remaining parts of said substrates.

13. A method of producing an interconnecting substrate for carrying a semiconductor device according to claim 12, further comprising the step of removing respective portions of said exposed electrode patterns by selective etching, as thick as prescribed, and thereby respective sunken sections are formed on reverse surfaces of said insulating layers.

14. A method of producing an interconnecting substrate for carrying a semiconductor device according to claim 11, further comprising the step of removing each of said first and said second substrates to expose said electrode patterns, after loading a semiconductor device thereon.

15. A method of producing an interconnecting substrate for carrying a semiconductor device according to claim 11, wherein, in the step of forming said first and said second electrode patterns, with conductive substrates being used as said first and said second substrates, resist layers which have opening patterns corresponding to the first and the second electrode patterns are formed on said first and said second substrates, respectively, and a deposition of metal is made inside of said opening patterns by the plating method, whereby said first and said second electrode patterns are formed.

16. A method of producing an interconnecting substrate for carrying a semiconductor device according to claim 15, wherein etching of said first and said second substrates is carried out, using said respective resist layers as masks, and thereby sunken sections corresponding to said opening patterns of the resist layers are formed on obverse surfaces of said substrates, respectively, and thereafter said first and said second electrode patterns are formed through a deposition of metal made on these sunken sections.

17. A method of producing an interconnecting substrate for carrying a semiconductor device, comprising the steps of:

forming an electrode pattern on a substrate;

forming, on said substrate, an insulating layer so as to cover said electrode pattern;

forming, in said insulating layer, a via hole to reach said electrode pattern; and

forming, on said insulating layer, a conductive substance layer so as to fill up said via hole, and then forming an interconnection pattern by patterning said conductive substance layer,

wherein said substrate is composed of one of a stainless steel board, a copper board, and a copper alloy board.