Function line and transistor array using the same

• US 7,339,192 B2
• Filed: 11/08/2002
• Issued: 03/04/2008
• Est. Priority Date: 12/06/2001
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Sakai, Osamu, Hatano, Akitsugu, Nishiki, Hirohiko
• Primary Examiner(s): Lee; Eugene
• Assistant Examiner(s): KRAIG, WILLIAM F
• Application Number:
  US10/496,801
• Publication Number:
  US 20050127363A1
• Time in Patent Office: 1,943 Days
• Field of Search: 257/59, 257/72, 257/E27.13, 257/E27.131, 349/41, 349/43, 438/34
• US Class Current: 257/72
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/144 Devices controlled by radiation

Abstract

An active-matrix substrate 30 includes multiple function lines 31, a structure for fixing up the arrangement of the function lines, a first conductive layer 43, a second conductive layer 42, multiple transistors 32 and multiple pixel electrodes 33. Each of the function lines 31 includes: a core 36, at least the surface of which has electrical conductivity; an insulating layer 37 that covers the surface of the core; and a semiconductor layer 38 that covers the insulating layer. Some portions of the first and second conductive layers 43 and 42 overlap with the respective semiconductor layers of the function lines but the others not. The transistors 32 are provided so as to have their channel defined as a region 44 in the semiconductor layer by the first and second conductive layers. The pixel electrodes 33 are electrically connected to the first conductive layer 43.

Claims

1. A function line comprising:

a core, at least the surface of which has electrical conductivity;

a first insulating layer covering the surface of the core;

a semiconductor layer covering the first insulating layer; and

a second insulating layer covering the semiconductor layer;

wherein

the core includes an electrically insulating fine wire and a conductive layer covering the fine wire.

2. The function line of claim 1, wherein the first insulating layer, the semiconductor layer and the second insulating layer cover substantially the entire core.

3. The function line of claim 1, wherein the core has a diameter of 5 μ

m to 1,000 μ

m.

4. The function line of claim 1, wherein the semiconductor layer is made of a transparent semiconductor.

5. The function line of claim 1, further comprising an opaque layer, which is provided to cover the second insulating layer.

6. The function line of claim 1, wherein the second insulating layer has light blocking ability.

7. The function line of claim 1, wherein the second insulating layer has a thickness of at least 10 nm.

8. A transistor array comprising:

a plurality of function lines, each including a core, an insulating layer covering the surface of the core, and a semiconductor layer covering the insulating layer;

a fixing structure for fixing the relative arrangement of the function lines; and

a plurality of transistors, each including a first conductive layer and a second conductive layer;

wherein

some portions of the first and second conductive layers overlap with the respective semiconductor layers of the function lines but not other portions;

the transistors are provided to have their channel defined as a region in the semiconductor layer by the first and second conductive layers; and

the core includes an electrically insulating fine wire and a conductive layer covering the fine wire.

9. The transistor array of claim 8, wherein the insulating layer and the semiconductor layer cover substantially the entire core.

10. The transistor array of claim 8, wherein the core has a diameter of 5 μ

m to 1,000 μ

m.

11. The transistor array of claim 8, wherein the semiconductor layer is made of a transparent semiconductor.

12. The transistor array of claim 8, further comprising an opaque layer, which is provided to cover the semiconductor layer.

13. The transistor array of claim 8, wherein the fixing structure includes a planarizing layer that fills in gaps between the function lines.

14. The transistor array of claim 8, wherein the core has a tensile strength of 100 MPa to 1,000 MPa along its length.

15. The transistor array of claim 8, wherein after the insulating layer and the semiconductor layer have been deposited to cover the core, the function lines are fixed with the fixing structure.

16. The transistor array of claim 15, wherein each of the function lines has a plurality of grooves that divide the semiconductor layer into multiple sections such that each of the plurality of grooves cross the length of the function line.

17. A transistor array comprising:

a plurality of function lines, each including a core, an insulating layer covering the surface of the core, and a semiconductor layer covering the insulating layer;

a fixing structure for fixing the relative arrangement of the function lines; and

a plurality of transistors, each including a first conductive layer and a second conductive layer;

wherein

at least the surface of the core is electrically conductive;

some portions of the first and second conductive layers overlap with the respective semiconductor layers of the function lines but not other portions;

the transistors are provided to have their channel defined as a region in the semiconductor layer by the first and second conductive layers; and

each said transistor further includes a third conductive layer, which is connected to the second conductive layer;

some portions of the third conductive layer overlap with the semiconductor layer but not other portions; and

the first conductive layer is sandwiched between the second and third conductive layers.

18. An active-matrix substrate comprising:

a plurality of function lines, each including a core, an insulating layer covering the surface of the core, and a semiconductor layer covering the insulating layer;

a fixing structure for fixing the relative arrangement of the function lines;

a plurality of transistors, each including a first conductive layer and a second conductive layer;

wherein

some portions of the first and second conductive layers overlap with the respective semiconductor layers of the function lines but not other portions;

the transistors are provided to have their channel defined as a region in the semiconductor layer by the first and second conductive layers;

a plurality of pixel electrodes are electrically connected to the first conductive layer; and

the core includes an electrically insulating fine wire and a conductive layer covering the fine wire.

19. An active-matrix substrate comprising:

a plurality of function lines, each including a core, an insulating layer covering the surface of the core, and a semiconductor layer covering the insulating layer;

a fixing structure for fixing the relative arrangement of the function lines;

a plurality of transistors, each including a first conductive layer and a second conductive layer;

wherein

at least the surface of the core is electrically conductive;

some portions of the first and second conductive layers overlap with the respective semiconductor layers of the function lines but not other portions;

the transistors are provided to have their channel defined as a region in the semiconductor layer by the first and second conductive layers;

a plurality of pixel electrodes are electrically connected to the first conductive layer;

each said transistor further includes a third conductive layer, which is connected to the second conductive layer;

some portions of the third conductive layer overlap with the semiconductor layer but not other portions; and

the first conductive layer is sandwiched between the second and third conductive layers.

20. The active-matrix substrate of claim 19, wherein

each of the function lines has a plurality of grooves that divide the semiconductor layer into multiple sections such that each of the plurality of grooves crosses the length of the function line.

21. An active-matrix substrate comprising:

a plurality of function lines, each including a core, an insulating layer covering the surface of the core, and a semiconductor layer covering the insulating layer;

a fixing structure for fixing the relative arrangement of the function lines;

a plurality of transistors, each including a first conductive layer and a second conductive layer;

wherein

at least the surface of the core is electrically conductive;

some portions of the first and second conductive layers overlap with the respective semiconductor layers of the function lines but not other portions;

the transistors are provided to have their channel defined as a region in the semiconductor layer by the first and second conductive layers;

a plurality of pixel electrodes are electrically connected to the first conductive layer; and

a plurality of storage capacitor lines, each including a core, the surface of which is electrically conductive, and an insulating layer covering the surface of the core, the storage capacitor lines overlapping with each other under the pixel electrodes.

22. The active-matrix substrate of claim 21, wherein the insulating layer and the semiconductor layer cover substantially the entire core.

23. The active-matrix substrate of claim 21, wherein the core is made of a metal.

24. The active-matrix substrate of claim 21, wherein the core has a diameter of 5 μ

m to 1,000 μ

m.

25. The active-matrix substrate of claim 21, wherein the semiconductor layer is made of a transparent semiconductor.

26. The active-matrix substrate of claim 21, wherein the core has a tensile strength of 100 MPa to 1,000 MPa along its length.

27. The active-matrix substrate of claim 21, wherein after the insulating layer and the semiconductor layer have been deposited to cover the core, the function lines are fixed with the fixing structure.

28. The active-matrix substrate of claim 21, wherein the fixing structure includes a planarizing layer that fills in gaps between the function lines.

29. The active-matrix substrate of claim 21, wherein the fixing structure includes a base substrate and an adhesive layer, the function lines being bonded onto the base substrate with the adhesive layer.

30. The active-matrix substrate of claim 29, wherein the base substrate has a plurality of grooves on the surface thereof, at least some of the function lines being bonded onto the base substrate with the adhesive layer to be embedded in the grooves.

31. The active-matrix substrate of claim 30, wherein the adhesive layer includes a light blocking substance.

32. The active-matrix substrate of claim 28, wherein the planarizing layer includes a light blocking substance.

33. The active-matrix substrate of claim 21, wherein the base substrate is made of a plastic with elasticity.

34. The active-matrix substrate of claim 21, wherein the second conductive layer is a data line.

35. The active-matrix substrate of claim 21, wherein the second conductive layer is a reference potential supply line.

36. A display device comprising:

the active-matrix substrate of claim 21;

a counter substrate; and

a display medium layer sandwiched between the substrates.

37. A method for fabricating an active-matrix substrate, the method comprising the steps of:

preparing a plurality of function lines, each including a core, an insulating layer covering the surface of the core, and a semiconductor layer covering the insulating layer;

fixing the relative arrangement of the function lines with a fixing structure;

providing a first conductive layer and a second conductive layer where some portions of the first and second conductive layers overlap with the respective semiconductor layers of the function lines but not other portions, thereby forming a plurality of transistors having their channel defined as a region in the semiconductor layer by the first and second conductive layers; and

forming a plurality of pixel electrodes that are electrically connected to the first conductive layer of the transistors;

wherein

at least the surface of the core is electrically conductive; and

the step of fixing the relative arrangement includes the steps of;

bonding the function lines onto the fixing structure with an adhesive layer; and

at least partially filling in gaps between the function lines with a planarizing layer.

38. The active-matrix substrate fabricating method of claim 37, wherein the first conductive layer of the transistors and the pixel electrodes are formed simultaneously.

39. A method for fabricating an active-matrix substrate, the method comprising the steps of:

preparing a plurality of function lines, each including a core, an insulating layer covering the surface of the core, and a semiconductor layer covering the insulating layer;

fixing the relative arrangement of the function lines with a fixing structure;

providing a first conductive layer and a second conductive layer where some portions of the first and second conductive layers overlap with the respective semiconductor layers of the function lines but not other portions, thereby forming a plurality of transistors having their channel defined as a region in the semiconductor layer by the first and second conductive layers; and

forming a plurality of pixel electrodes that are electrically connected to the first conductive layer of the transistors;

wherein

at least the surface of the core is electrically conductive; and

the step of fixing the relative arrangement includes the steps of;

pressing the function lines and a plurality of storage capacitor lines onto a plastically deformable layer, thereby embedding the function lines and the storage capacitor lines to a predetermined depth in the plastically deformable layer;

burying the exposed portions of the function lines and the storage capacitor lines in a curable resin on the base substrate; and

curing the curable resin and then removing the plastically deformable layer.