Metallization performance in electronic devices
First Claim
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1. An electronic device having design rule of 0.9 μ
- m or finer comprising
1) an electrical interconnect configured to electrically connect discrete regions of said electronic device to produce a desired function of said electronic device, said electrical interconnect comprising a patterned metal having two transverse edges and
2) a material underlying said electrical interconnect wherein the surface of said material includes non-planarities having a height of at least 0.02 μ
m such that at least 80 percent of the distances between nearest neighbors of said non-planarities that are within 0.1 μ
m of at least one of said transverse edges of said interconnect is about 100 μ
m or less.
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Abstract
Phenomena such as electromigration and stress-induced migration occurring in metal interconnects of devices such as integrated circuits are inhibited by use of underlying non-planarities. Thus the material underlying the interconnect is formed to have non-planarities typically of at least 0.02 μm in height and advantageously within 100 μm of another such non-planarity. Such non-planarities, it is contemplated, reduce grain boundary movement in the overlying interconnect with a concomitant reduction in void aggregation.
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Citations
27 Claims
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1. An electronic device having design rule of 0.9 μ
- m or finer comprising
1) an electrical interconnect configured to electrically connect discrete regions of said electronic device to produce a desired function of said electronic device, said electrical interconnect comprising a patterned metal having two transverse edges and
2) a material underlying said electrical interconnect wherein the surface of said material includes non-planarities having a height of at least 0.02 μ
m such that at least 80 percent of the distances between nearest neighbors of said non-planarities that are within 0.1 μ
m of at least one of said transverse edges of said interconnect is about 100 μ
m or less. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
- m or finer comprising
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10. An integrated circuit including an electronic device having design rule of 0.9 μ
- m or finer comprising
1) an electrical interconnect configured to electrically connect discrete regions of said integrated circuit to produce a desired function of said integrated circuit, said electrical interconnect comprising a patterned metal having two transverse edges and
2) a material underlying said electrical interconnect wherein the surface of said material includes non-planarities having a height of at least 0.02 μ
m such that at least 80 percent of the distances between nearest neighbors of said non-planarities that are within 0.1 μ
m of at least one of said transverse edges of said interconnect is about 100 μ
m or less. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
- m or finer comprising
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19. A wafer including an electronic device having design rule of 0.9 μ
- m or finer comprising
1) an electrical interconnect configured to electrically connect discrete regions of said electronic device to produce a desired function of said electronic device, said electrical interconnect comprising a patterned metal having two transverse edges and
2) a material underlying said electrical interconnect wherein the surface of said material includes non-planarities having a height of at least 0.02 μ
m such that at least 80 percent of the distances between nearest neighbors of said non-planarities that are within 0.1 μ
m of at least one of said transverse edges of said interconnect is about 100 μ
m or less. - View Dependent Claims (20, 21, 22, 23, 25, 26, 27)
- m or finer comprising
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24. The device of clam 19 wherein said metal comprises gold or silver.
Specification
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Current AssigneeBell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
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Original AssigneeAgere Systems Incorporated (Broadcom, Inc.)
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InventorsDesko, John C. Jr., Ryan, Vivian, Lian, Sean, Jones, Bailey R., Molloy, Simon John
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Primary Examiner(s)Lee; Eugene
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Application NumberUS10/919,591Publication NumberTime in Patent Office1,295 DaysField of Search257/767, 257/E21.577, 257/775, 257/762, 257/773, 257/776US Class Current257/775CPC Class CodesH01L 23/5283 Cross-sectional geometryH01L 2924/00 Indexing scheme for arrange...H01L 2924/0002 Not covered by any one of g...
