Analog-to-digital converter without track-and-hold

• US 7,339,512 B2
• Filed: 06/27/2006
• Issued: 03/04/2008
• Est. Priority Date: 09/17/2004
• Status: Active Grant

• Current Assignee: EDGEWATER WIRELESS SYSTEMS INC.
• Original Assignee: Edgewater Computer Systems Inc.
• Inventors: Gulati, Kush, Munoz, Carlos, Pulincherry, Anurag, Peng, Mark
• Primary Examiner(s): Nguyen, Linh V.
• Application Number:
  US11/475,721
• Publication Number:
  US 20070035432A1
• Time in Patent Office: 616 Days
• Field of Search: 341/155, 341/161, 341/122, 341/172
• US Class Current: 341/172
• CPC Class Codes: H03M 1/0695 using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
• CPC Class Codes: H03M 1/168 and delivering the same number of bits

Abstract

A system and method for converting an analog signal to a digital signal is provided. The analog to digital conversion is achieved without a dedicated sample-and-hold circuit. An ADC stage, preferably the front-end stage in the case of a pipeline ADC, samples the input voltage within a quantizer and within a residue generator. The sampling is performed with associated clocking signals and with switch capacitors also fulfilling the comparison with threshold voltages, within the quantizer and the generation of a residue signal within the residue generator.

Claims

1. An analog-to-digital converter comprising:

an input to receive an input analog signal;

a quantizer comprising at least one comparator subcircuit, the comparator subcircuit comprising at least a threshold capacitor switch coupled to the input for sampling the input analog signal during a quantizer sampling phase and switch coupled to a threshold voltage for producing a digital output signal based on a comparison of the sampled input analog signal to the threshold voltage during a comparison period; and

a residue generator coupled to the quantizer, the residue generator comprising a plurality of reference capacitors and a feedback capacitor switch coupled to the input, for sampling the input analog signal during a reference generator sampling phase different from the quantizer sampling phase, said reference capacitors being also switched coupled to a plurality of reference voltages based on settings received from the quantizer during an amplify phase and said feedback capacitor wrapping around an op-amp during said amplify phase, for producing a residue analog output signal, residue generator sampling characteristics substantially matching quantizer sampling characteristics.

2. The converter as claimed in claim 1, wherein a degree of matching of the sampling characteristics is selected at least in part based upon an expected frequency range of the input signal.

6. A pipelined analog-to-digital converter comprising a first stage, one or more intermediate stages each of which receives as input a residue signal output from an immediately preceding stage, a final stage which converts a residue output signal from a next-to-final stage into a corresponding digital signal and correction logic which receives each stage'"'"'s output and generates a corresponding digital word;

and at least the first stage being an analog-to-digital converter according to claim 1.

7. The analog-to-digital converter of claim 6, wherein the analog-to-digital converter is selected from among a pipeline converter, a cyclic converter, a pipeline sigma-delta converter, an error-correcting successive approximation converter, and a two-step converter.

3. A method of converting an input analog voltage into a digital voltage comprising:

within a quantizer, using a plurality of threshold capacitors switch coupled to an input for sampling the input analog voltage during a quantizer sampling phase and switch coupled to a plurality of threshold voltages for comparing the threshold voltages with the sampled input analog voltage; and

within a residue generator connected to the quantizer, using a plurality of reference capacitor switch coupled to the input for sampling the input analog voltage during a residue generator sampling phase different from the quantizer sampling phase and switch coupled to a plurality of reference voltages in response to settings received from the quantizer for producing a residue signal, residue generator sampling characteristics substantially matching quantizer sampling characteristics.

4. The method as claimed in claim 3 wherein the sampling characteristics are matched at least in part based upon an expected frequency range of the input analog voltage signal.

5. The analog-to-digital converter of claim 3 wherein the matched sampling characteristics include the bandwidths of the sampling networks.