Inverter bridge short-circuit protection scheme

• US 7,339,803 B2
• Filed: 04/09/2004
• Issued: 03/04/2008
• Est. Priority Date: 04/09/2004
• Status: Active Grant

• Current Assignee: Eaton Intelligent Power Limited (Eaton Corporation PLC.)
• Original Assignee: Eaton Corp. (Wisconsin) (Eaton Corporation PLC.)
• Inventors: Nojima, Geraldo
• Primary Examiner(s): Patel; Rajnikant B.
• Application Number:
  US10/558,951
• Publication Number:
  US 20060245222A1
• Time in Patent Office: 1,425 Days
• Field of Search: 363 34- 41, 363/65, 363/68, 363/71, 363/95, 363/132, 363/98, 361/79, 361/91.06, 361/86, 361/91.01
• US Class Current: 363/37
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 1/38 Means for preventing simultaneous conduction of switches
• CPC Class Codes: H02M 7/487 Neutral point clamped inverters
• CPC Class Codes: H02M 7/53871 with automatic control of output voltage or current

Abstract

A fault handling system for short circuit recovery in three-phase multiple-level inverter bridges, used to drive inductive loads, to assure a proper sequence for turning-off switches in the inverter bridge. Switches are selected for use in the inverter bridge so that outer switches toward the most positive and most negative bus voltage levels of the inverter bridge have lower transconductances than inner switches closest to an output phase of the inverter bridge. Additionally, driver cards driving outer switches utilize lower magnitude excitation control signals than driver cards driving inner switches. Driver cards driving outer switches, when detecting desaturation of an on-state switch, are set to automatically command the outer switch to an off-state, whereas driver cards driving inner switches wait for instructions from a controller before taking action.

Claims

1. A three-phase multiple-level inverter bridge having three branches, each branch providing one phase of the three-phase output for driving an inductive load, the multiple-level inverter bridge having “

L”

bus voltage levels (L≧

3), wherein two of the L levels are a most-negative bus voltage and a most-positive bus voltage, any intermediate bus voltage levels being differentiated from other bus voltage levels by a difference of the most-positive bus voltage and the most-negative bus voltage, divided by (L−

1),

each branch comprising two half-branches, a first one-half branch comprising (L−

1) switches connected in series between the most-positive bus voltage and the phase output, and a second one-half branch comprising (L−

1) switches connected in series between the most-negative bus voltage and the phase output,

each half branch comprising;

an outermost switch of the (L−

1) switches which is the switch connected to the most-positive bus voltage or the most-negative bus voltage;

an innermost switch of the (L−

1) switches which is the switch connected to the phase output; and

if L>

3, (L−

3) intermediate switches of the (L−

1) switches connected in series between the innermost switch and the outermost switch,

wherein;

each of the (L−

1) switches has a transconductance, and is configured to be driven by a control signal, and

each outermost switch has a lower transconductance than a transconductance of the innermost switch of the same half branch, and

if L>

3, each intermediate switch of a half branch has a transconductance that is no greater than that of an inner next switch in the series, connected toward the phase output, and is no less than that of an outer next switch in the series, connected toward the most-negative bus voltage or the most-positive bus voltage.

2. A three-phase multiple-level inverter bridge according to claim 1, wherein each intermediate switch of a half branch has a transconductance that is less than that of an inner next switch in the series, connected toward the phase output, and is greater than that of an outer next switch in the series, connected toward the most-negative bus voltage or the most-positive bus voltage.

3. A three-phase multiple-level inverter bridge according to claim 1, wherein each switch of the (L−

1) switches is selected from the group consisting of a insulated gate bipolar transistor (IGBT), a field effect transistor (FET), and a bipolar junction transistor (BJT).

4. A method of preparing switches for a three-phase multiple-level inverter bridge having three branches, each branch providing one phase of the three-phase output for driving an inductive load, the multiple-level inverter bridge having “

L”

bus voltage levels (L≧

3), wherein two of the L levels are a most-negative bus voltage and a most-positive bus voltage, any intermediate bus voltage levels being differentiated from other bus voltage levels by a difference of the most-positive bus voltage and the most-negative bus voltage, divided by (L−

1),

each branch comprising two half-branches, a first one-half branch comprising (L−

1) switches connected in series between the most-positive bus voltage and the phase output, and a second one-half branch comprising (L−

1) switches connected in series between the most-negative bus voltage and the phase output,

each half branch having an outermost switch of the (L−

1) switches which is the switch connected to the most-positive bus voltage or the most-negative bus voltage, each half branch having an innermost switch of the (L−

1) switches which is the switch connected to the phase output,

each of the (L−

1) switches having a transconductance, and configured to be driven by a control signal, and

each outermost switch having a lower transconductance than a transconductance of the innermost switch of the same half branch,

wherein if L>

3, there are (L−

3) intermediate switches of the (L−

1) switches connected in series between the innermost switch and the outermost switch, each intermediate switch of a half branch having a transconductance that is no greater than that of a inner next switch in the series, connected toward the phase output, and is no less than that of an outer next switch in the series, connected toward the most-negative bus voltage or the most-positive bus voltage,

the method comprising;

determining the transconductance of at least 6(L−

1) switches;

selecting, for each half branch, an outer switch and an inner switch, so that said outer switch has a lower transconductance than said inner switch; and

selecting, if L>

3, for each half branch, each intermediate switch so that a transconductance of the respective intermediate switch is no greater than that of an inner next switch to be connected toward the phase output, and is no less than that of an outer next switch to be connected toward the most-negative bus voltage or the most-positive bus voltage.

5. A method according to claim 4, further comprising:

for each one-half branch, after selecting the inner switch, the outer switch, and if L>

3, any intermediate switches, labeling the switches to designate their relative position in the respective one half branch.

6. A method according to claim 4, wherein selecting each intermediate switch further comprises selecting each intermediate switch of a half branch to have a transconductance that is less than that of an inner next switch to be connected toward the phase output, and is greater than that of an outer next switch to be connected toward the most-negative bus voltage or the most-positive bus voltage.

7. A method according to claim 6, further comprising:

for each one half branch, after selecting the inner switch, the outer switch, and if L>

3, any intermediate switches, labeling the switches to designate their relative position in the respective one half branch.

8. A method according to claim 6, further comprising:

matching, for each half branch, an outer switch to an outer-switch driving circuit configured to provide a first excitation control signal to drive the outer switch to an on-state or an off-state;

matching, for each half branch, an inner switch to an inner-switch driving circuit configured to provide a second excitation control signal to drive the inner switch to an on-state or an off-state,

wherein the outer-switch driving circuit and the inner-switch driving circuit are selected or set so that said first excitation control signal, when driving the outer switch to an on-state, is smaller in magnitude than said second excitation control signal, when driving the inner switch to an on-state; and

if L>

3, then for each half branch and for each intermediate switch within the respective half branch, matching the intermediate switch to a respective intermediate-switch driving circuit configured to provide an intermediate excitation control signal to drive the intermediate switch to an on-state or an off-state, wherein each intermediate-switch driving circuit is selected or set so that when driving the intermediate switch to an on-state, the intermediate excitation control signal is no greater in magnitude than that of an excitation control signal used to drive the respective inner next switch to an on-state, and is no less than that of an excitation control signal used to drive the respective outer-next switch to an on-state.

9. A method according to claim 4, further comprising:

matching, for each half branch, an outer switch to an outer-switch driving circuit configured to provide a first excitation control signal to drive the outer switch to an on-state or an off-state;

matching, for each half branch, an inner switch to an inner-switch driving circuit configured to provide a second excitation control signal to drive the inner switch to an on-state or an off-state,

wherein the outer-switch driving circuit and the inner-switch driving circuit are selected or set so that said first excitation control signal, when driving the outer switch to an on-state, is smaller in magnitude than said second excitation control signal, when driving the inner switch to an on-state; and

if L>

3, then for each half branch and for each intermediate switch within the respective half branch, matching the intermediate switch to a respective intermediate-switch driving circuit configured to provide an intermediate excitation control signal to drive the intermediate switch to an on-state or an off-state, wherein each intermediate-switch driving circuit is selected or set so that when driving the intermediate switch to an on-state, the intermediate excitation control signal is less in magnitude than that of an excitation control signal used to drive the respective inner next switch to an on-state, and is greater than that of an excitation control signal used to drive the respective outer-next switch to an on-state.

10. A method according to claim 4, wherein each selected innermost, outermost, and intermediate switch is selected from the group consisting of a insulated gate bipolar transistor (IGBT), a field effect transistor (FET), and a bipolar junction transistor (BJT).

11. A system comprising:

a three-phase multiple-level inverter bridge having three branches, each branch providing one phase of the three-phase output for driving an inductive load, the multiple-level inverter bridge having “

L”

bus voltage levels (L≧

3), wherein two of the L levels are a most-negative bus voltage and a most-positive bus voltage, any intermediate bus voltage levels being differentiated from other bus voltage levels by a difference of the most-positive bus voltage and the most-negative bus voltage, divided by (L−

1),

each branch comprising two half-branches, a first one-half branch comprising (L−

1) switches connected in series between the most-positive bus voltage and the phase output, and a second one-half branch comprising (L−

1) switches connected in series between the most-negative bus voltage and the phase output,

each half branch having an outermost switch of the (L−

1) switches which is the switch connected to the most-positive bus voltage or the most-negative bus voltage,

each half branch having an innermost switch of the (L−

1) switches which is the switch connected to the phase output,

wherein if L>

3, there are (L−

3) intermediate switches of the (L−

1) switches connected in series between the innermost switch and the outermost switch, and

a plurality of driving circuits configured to drive switches of the inverter bridge, each of the inverter bridge switches having its own driving circuit, and each driving circuit providing an excitation control signal driving the respective switch to an on-state or an off-state,

wherein each outermost switch of each half branch is driven to an on-state by a lower-magnitude excitation control signal, than a magnitude of an excitation control signal used to drive an innermost switch of the same half branch to an on-state,

wherein, if L>

3, each intermediate switch of a half branch is driven to an on-state by an excitation control signal that is no greater in magnitude than that of an excitation control signal used to drive an inner next switch connected toward the phase output to an on-state, and is no less than that of an excitation control signal used to drive an outer next switch connected toward the most-negative bus voltage or the most-positive bus voltage to an on-state.

12. A system of according to claim 11, wherein:

each of the (L−

1) switches has a transconductance, and

each outermost switch has a lower transconductance than a transconductance of the innermost switch of the same half branch,

if L>

3, each intermediate switch of a half branch has a transconductance that is less than that of an inner next switch connected toward the phase output, and is greater than that of an outer next switch connected toward the most-negative bus voltage or the most-positive bus voltage.

13. A system of according to claim 11, wherein if L>

3, each intermediate switch of a half branch is driven to an on-state by an excitation control signal that is less in magnitude than that of an excitation control signal used to drive an inner next switch connected toward the phase output to an on-state, and is greater than that of an excitation control signal used to drive an outer next switch connected toward the most-negative bus voltage or the most-positive bus voltage to an on-state.

14. A system of according to claim 13, wherein:

each of the (L−

1) switches has a transconductance, and

each outermost switch has a lower transconductance than a transconductance of the innermost switch of the same half branch,

if L>

3, each intermediate switch of a half branch has a transconductance that is no greater than that of a inner next switch connected toward the phase output, and is no less than that of an outer next switch connected toward the most-negative bus voltage or the most-positive bus voltage.

15. A system of according to claim 13, wherein:

each of the (L−

1) switches has a transconductance, and

each outermost switch has a lower transconductance than a transconductance of the innermost switch of the same half branch,

if L>

3, each intermediate switch of a half branch has a transconductance that is less than that of a inner next switch connected toward the phase output, and is greater than that of an outer next switch connected toward the most-negative bus voltage or the most-positive bus voltage.

16. A system according to claim 11, wherein for each half branch, each switch of the (L−

1) switches is selected from the group consisting of a insulated gate bipolar transistor (IGBT), a field effect transistor (FET), and a bipolar junction transistor (BJT),

wherein if the (L−

1) switches are IGBTs, each excitation control signal is a voltage applied between a gate and an emitter of a respective IGBT,

wherein if the (L−

1) switches are FETs, each excitation control signal is a voltage applied between a gate and a source of a respective FET, and

wherein if the (L−

1) switches are BJTs, each excitation control signal is a current applied between a base and an emitter of a respective BJT.

17. A system comprising:

a three-phase multiple-level inverter bridge having three branches, each branch providing one phase of the three-phase output for driving an inductive load, the multiple-level inverter bridge having “

L”

bus voltage levels (L≧

3), wherein two of the L levels are a most-negative bus voltage and a most-positive bus voltage, any intermediate bus voltage levels being differentiated from other bus voltage levels by a difference of the most-positive bus voltage and the most-negative bus voltage, divided by (L−

1),

each branch comprising two half-branches, a first one-half branch comprising (L−

1) switches connected in series between the most-positive bus voltage and the phase output, and a second one-half branch comprising (L−

1) switches connected in series between the most-negative bus voltage and the phase output,

each half branch having an outermost switch of the (L−

1) switches which is the switch connected to the most-positive bus voltage or the most-negative bus voltage,

each half branch having an innermost switch of the (L−

1) switches which is the switch connected to the phase output, and

if L>

3, each half branch having (L−

3) intermediate switches of the (L−

1) switches connected in series between the innermost switch and the outermost switch; and

a plurality of driving circuits configured to drive switches of the inverter bridge, each of the inverter bridge switches having its own driving circuit, and each driving circuit providing an excitation control signal driving the respective switch to an on-state or an off-state;

a plurality of monitoring circuits, each of the inverter bridge switches having its own monitoring circuit monitoring either a voltage across a respective switch in an on-state or a current through a respective switch in an on-state;

a plurality of overload condition detecting circuits, each of the inverter bridge switches having its own overload condition detecting circuit, detecting an overload condition by comparing the monitored voltage or current of the respective switch in the on-state with a threshold level;

a three-phase multiple-level inverter controller, commanding each driving circuit when to output an excitation control signal to drive a respective switch an on-state or an off-state;

wherein each driving circuit providing the excitation control signal to a respective outermost switch, upon detection of an overload condition of the respective outermost switch, automatically drives the respective outermost switch to an off-state, and the overload detecting circuit of the respective outermost switch signals to said three-phase multiple-level inverter controller that the overload condition has been detected,

wherein each overload detecting circuit of a respective innermost switch, upon detection of an overload condition of the respective innermost switch, signals to said three-phase multiple-level inverter controller that the overload condition has been detected, and the driving circuit providing the excitation control signal to the respective innermost switch waits for instructions from said three-phase multiple-level inverter controller as to whether to leave the innermost switch in an on-state or to drive the innermost switch to an off-state.

18. A system according to claim 17, wherein L>

3, and

wherein each overload detecting driving circuit of a respective intermediate switch, upon detection of an overload condition of the respective intermediate switch, signals to said three-phase multiple level inverter controller that the overload condition has been detected, and the driving circuit providing the excitation control signal to the respective intermediate switch waits for instructions from said three-phase multiple-level inverter controller as to whether to leave the intermediate switch in an on-state or to drive the intermediate switch to an off-state.

19. A system according to claim 17, wherein L>

3,

wherein each driving circuit providing the excitation control signal to a respective intermediate switch, upon detection of an overload condition of the respective intermediate switch, automatically drives the respective intermediate switch to an off-state, and the overload detecting circuit of the respective intermediate switch signals to said three-phase multiple-level inverter controller that the overload condition has been detected,

wherein each outermost switch of a half branch is driven to an on-state by a lower-magnitude excitation control signal than a magnitude of an excitation control signal used to drive an innermost switch of the same half branch to an on-state,

each intermediate switch of a half branch is driven to an on-state by an excitation control signal that is smaller in magnitude than that excitation control signal used to drive an inner next switch connected toward the phase output to an on-state, and is greater in magnitude than that excitation control signal used to drive an outer next switch connected toward the most-negative bus voltage or the most-positive bus voltage to an on-state,

each of the (L−

1) switches has a transconductance,

each outermost switch has a lower transconductance than a transconductance of the innermost switch of the same half branch, and

each intermediate switch of a half branch has a transconductance that is less than that of a inner next switch connected toward the phase output, and is greater than that of an outer next switch connected toward the most-negative bus voltage or the most-positive bus voltage.

20. A system according to claim 17, wherein each switch of the (L−

1) switches of each half branch is selected from the group consisting of a insulated gate bipolar transistor (IGBT), a field effect transistor (FET), a bipolar junction transistor (BJT), silicon controlled rectifier (SCR), insulated gate control thyristor (IGCT), gate turn-off thyristor (GTO), and metal-oxide silicon controlled thyristor (MCT),

wherein if the switches are IGBTs, FETs, or BJTs, each monitoring circuit monitors a voltage across the respective switch in the on-state, and

wherein if the switches are SCRs, IGCTs, GTOs, or MCTs, each monitoring circuit monitors a current through the respective switch in the on-state.

21. A system according to claim 20, wherein if the switches are IGBTs, FETS, or BJTs, said threshold level is a desaturation voltage value per switch, and when the monitored voltage in the on-state is above said threshold level, the switch is considered desaturated, thereby indicating the overload condition.

22. A system according to claim 20, wherein if the switches are SCRs, IGCTs, GTOs, or MCTs, said threshold level is a maximum rated short circuit current (I_sc) per switch, and when the monitored current in the on-state is above said threshold level, the switch is considered desaturated, thereby indicating the overload condition.