Method and apparatus for reading data from nonvolatile memory

• US 7,339,846 B2
• Filed: 07/14/2006
• Issued: 03/04/2008
• Est. Priority Date: 07/14/2006
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lin, Yung Feng, Lin, Yu Shen
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US11/457,686
• Publication Number:
  US 20080013379A1
• Time in Patent Office: 599 Days
• Field of Search: 365/203, 365/196, 365/230.03
• US Class Current: 365/203
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

Roughly described, a memory includes first and second target memory cells in a plurality of electrically adjacent memory cells all sharing a word line. The two target memory cells are separated from each other by at least one additional memory cell, and first current path terminals of the target memory cells bracket second current path terminals of the target memory cells electrically along the word line. The two target memory cells are read by connecting the first current path terminals of the two target memory cells to ground, precharging the second current path terminals of the two target memory cells to respective precharged states, and while both second current path terminals are in their respective precharged states, initiating a sense operation to read both the first and second target memory cells substantially simultaneously.

Claims

1. A method for reading memory cells in a plurality of electrically adjacent memory cells all sharing a word line in a memory array, the plurality of cells including a first cell and a last cell, each of the cells in the plurality sharing a bit line with each of its adjacent cells, the first and last cells being further connected to first and last bit lines, respectively, which are not shared with any other cells in the plurality,

the bit lines including a first group of at least one adjacent bit line and a last group of at least one adjacent bit line distinct from the first group, the first group being adjacent to the first bit line and the last group being adjacent to the last bit line,

the method comprising the steps of:

precharging both first and last common bit lines to respective precharged states, the first common bit line being the bit line in the first group that is shared with the first cell in the plurality, and the last common bit line being the bit line in the last group that is shared with the last cell in the plurality; and

while both the first and last common bit lines are in their respective precharged states, initiating a sense operation to read both the first and last cells substantially simultaneously,

wherein the step of precharging both the first and last common bit lines to respective precharged states comprises the step of precharging to respective precharge states all of the bit lines in the first and last groups of bit lines,

and wherein the step of precharging to respective precharge states all of the bit lines in the first and last groups of bit lines comprises the steps of;

precharging to respective precharge states all of the bit lines in the first group of bit lines to a first precharge voltage; and

precharging to respective precharge states all of the bit lines in the last groups of bit lines to a second precharge voltage.

2. A method according to claim 1, wherein the bit lines shared among cells in the plurality further include a middle group of at least one bit line, the middle group being distinct from but adjacent to both the first and last groups, and

further comprising the step of floating all the bit lines in the middle group during the steps of precharging and initiating a sense operation.

3. A method according to claim 1, further comprising the steps of connecting all of the bit lines in the first group to a first common node and connecting all of the bit lines in the last group to a second common node,

wherein the step of precharging both the first and last common bit lines to respective precharged states comprises the steps of connecting the first common node to a first precharge source and connecting the second common node to a second precharge source,

and wherein the step of initiating a sense operation to read both the first and last cells substantially simultaneously comprises the steps of:

disconnecting the first common node from the first precharge source and connecting it to a first sense amplifier; and

disconnecting the second common node from the second precharge source and connecting it to a second sense amplifier.

4. A method according to claim 1, further comprising the step of discharging all of the bit lines in the first and last groups prior to the step of precharging.

5. A memory system comprising:

a plurality of electrically adjacent memory cells all sharing a word line in a memory array, the plurality of cells including a first cell and a last cell, each of the cells in the plurality sharing a bit line with each of its adjacent cells, the first and last cells being further connected to first and last bit lines, respectively, which are not shared with any other cells in the plurality,

the bit lines including a first group of at least one adjacent bit line and a last group of at least one adjacent bit line distinct from the first group, the first group being adjacent to the first bit line and the last group being adjacent to the last bit line,

the bit line in the first group that is shared with the first cell in the plurality being a first common bit line, and the bit line in the last group that is shared with the last cell in the plurality being a last common bit line;

means for precharging both the first and last common bit lines to respective precharged states; and

means for initiating a sense operation to read both the first and last cells substantially simultaneously, the sense operation being initiated while both the first and last common bit lines are in their respective precharged states.

6. A memory system including a control unit for reading memory cells in a plurality of electrically adjacent memory cells all sharing a word line in a memory array, the plurality of cells including a first cell and a last cell, each of the cells in the plurality sharing a bit line with each of its adjacent cells, the first and last cells being further connected to first and last bit lines, respectively, which are not shared with any other cells in the plurality,

the bit lines including a first group of at least one adjacent bit line and a last group of at least one adjacent bit line distinct from the first group, the first group being adjacent to the first bit line and the last group being adjacent to the last bit line,

the bit line in the first group that is shared with the first cell in the plurality being a first common bit line, and the bit line in the last group that is shared with the last cell in the plurality being a last common bit line,

wherein the control unit generates control signals which cause:

both the first and last common bit lines to be precharged to respective precharged states; and

while both the first and last common bit lines are in their respective precharged states, a sense operation to be initiated to read both the first and last cells substantially simultaneously.

7. A method for reading first and second target memory cells in a plurality of electrically adjacent memory cells all sharing a word line in a memory array, the first and second target memory cells each having respective first and second current path terminals, the second current path terminals of the first and second target memory cells being separated from each other electrically along the word line by at least one additional memory cell, and the first current path terminals of the first and second target memory cells bracketing the second current path terminals of the first and second target memory cells electrically along the word line, comprising the steps of:

connecting the first current path terminal of the first target memory cell through selection circuitry to ground;

connecting the second current path terminal of the first target memory cell through selection circuitry to a first sensing node;

connecting the first current path terminal of the second target memory cell through selection circuitry to ground;

connecting the second current path terminal of the second target memory cell through selection circuitry to a second sensing node;

precharging the first sensing node to a first precharge voltage;

precharging the second sensing node to a second precharge voltage; and

while both the first and second sensing nodes are in their respective precharged states, initiating a sense operation to read both the first and second target memory cells substantially simultaneously.

8. A memory system comprising:

a plurality of electrically adjacent memory cells all sharing a word line in a memory array, the plurality of memory cells including first and second target memory cells, the first and second target memory cells each having respective first and second current path terminals, the second current path terminals of the first and second target memory cells being separated from each other electrically along the word line by at least one additional memory cell, and the first current path terminals of the first and second target memory cells bracketing the second current path terminals of the first and second target memory cells electrically along the word line;

means for connecting the first current path terminal of the first target memory cell to ground;

means for connecting the second current path terminal of the first target memory cell to a first sensing node;

means for connecting the first current path terminal of the second target memory cell to ground;

means for connecting the second current path terminal of the second target memory cell to a second sensing node;

means for precharging both the first and second sensing nodes to respective precharged states; and

means for initiating a sense operation to read both the first and second target memory cells substantially simultaneously, the sense operation being initiated while both the first and second sensing nodes are in their respective precharged states.

9. A memory system including a control unit for reading first and second target memory cells in a plurality of electrically adjacent memory cells all sharing a word line in a memory array, the first and second target memory cells each having respective first and second current path terminals, the second current path terminals of the first and second target memory cells being separated from each other electrically along the word line by at least one additional memory cell, and the first current path terminals of the first and second target memory cells bracketing the second current path terminals of the first and second target memory cells electrically along the word line, wherein the control unit generates control signals which cause:

the first current path terminal of the first target memory cell to be connected through selection circuitry to ground;

the second current path terminal of the first target memory cell to be connected through selection circuitry to a first sensing node;

the first current path terminal of the second target memory cell to be connected through selection circuitry to ground;

the second current path terminal of the second target memory cell to be connected through selection circuitry to a second sensing node;

both the first and second sensing nodes to be precharged to respective precharged states; and

while both the first and second sensing nodes are in their respective precharged states, a sense operation to be initiated to read both the first and second target memory cells substantially simultaneously.

10. A memory system according to claim 9, further comprising:

a first precharging/sensing circuit connected to the first sensing node, the first precharging/sensing circuit including first circuitry which precharges the first sensing node to a first precharge state in response to a signal from the control unit, and which senses the state of the first target memory cell in response to a signal from the control unit; and

a second precharging/sensing circuit connected to the second sensing node, the second precharging/sensing circuit including second circuitry which precharges the second sensing node to a second precharge state in response to a signal from the control unit, and which senses the state of the second target memory cell in response to a signal from the control unit.

11. A memory system according to claim 10,

wherein the first circuitry includes a first precharging unit and a first sensing unit which connect alternatively to the first sensing node in response to signals from the control unit,

and wherein the second circuitry includes a second precharging unit and a second sensing unit which connect alternatively to the second sensing node in response to signals from the control unit.