Anti-fuse latch circuit and method including self-test

• US 7,339,848 B1
• Filed: 01/30/2006
• Issued: 03/04/2008
• Est. Priority Date: 11/03/2005
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Stansell, Galen, Jenne, Frederick, Kouznetzov, Igor, Fox, Ken
• Primary Examiner(s): Dinh, Son
• Application Number:
  US11/343,341
• Time in Patent Office: 764 Days
• Field of Search: 365/225.7, 365/200, 365/201
• US Class Current: 365/225.7
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory

Abstract

A programmable latch circuit (100) can include a programmable data circuit (104) with a data load path (116) that can enable a data value to be recalled into a volatile latch (102). A data load path (116) can be formed with devices (P100-P102) having low threshold voltages. Data can be loaded via data load path at lower power supply voltages levels, such as on power-on and/or reset operations. Other embodiments disclose, self-test circuits, full redundancy capabilities, and resistors for limiting current draw in an anti-fuse program operation.

Claims

1. A programmable latch circuit, comprising:

at least one anti-fuse device that provides a first impedance in an unprogrammed state and a second impedance in a programmed state, the second impedance being less than the first impedance;

at least one program path coupled between a node of a volatile latch circuit and the at least one anti-fuse device that is enabled in a program operation that establishes a state of the anti-fuse device; and

at least one data load path coupled between the node of the volatile latch circuit and the anti-fuse device in parallel with the at least one program path, the at least one data load path comprising a source-drain path of at least one p-channel insulated gate field effect transistor (IGFET).

2. The programmable latch circuit of claim 1, further including:

a resistor formed in the same substrate as the anti-fuse device coupled between the anti-fuse device and a program voltage node.

3. The programmable latch circuit of claim 1, wherein:

the at least one anti-fuse device includes at least a first primary anti-fuse device and a first redundant anti-fuse device;

the at least one program path includes

a first primary program path coupled between a first node of the volatile latch circuit and the first primary anti-fuse device, and

a first redundant program path coupled between the first node of the volatile latch circuit and the first redundant anti-fuse device; and

the at least one data load path includes

a first primary data load path coupled between the first node of the volatile latch circuit and the first primary anti-fuse device, and

a first redundant data load path coupled between the first node of the volatile latch circuit and the first redundant anti-fuse device.

4. The programmable latch circuit of claim 3, wherein:

the at least one anti-fuse device further includes a second primary anti-fuse device and a second redundant anti-fuse device;

the at least one program path further includes

a second primary program path coupled between a second node of the volatile latch circuit and the second primary anti-fuse device, and

a second redundant program path coupled between the second node of the volatile latch circuit and the second redundant anti-fuse device; and

at least one data load path further includes

a second primary data load path coupled between the second node of the volatile latch circuit and the second primary anti-fuse device, and

a second redundant data load path coupled between the second node of the volatile latch circuit and the second redundant anti-fuse device.

5. The programmable latch circuit of claim 1, wherein:

the at least one data load path consists of a plurality of p-channel IGFETs having source-drain paths arranged in series between the node of the volatile latch circuit and the anti-fuse device.

6. The programmable latch circuit of claim 1, wherein:

the at least one program path consists of a plurality of n-channel IGFETs having source-drain paths arranged in series between the node of the volatile latch circuit and the anti-fuse device.

7. The programmable latch circuit of claim 1, further including:

the at least one program path is coupled to a first node of the volatile latch circuit;

the at least one data load path is coupled to the first node of the volatile latch; and

an anti-fuse test circuit coupled between the first node of the volatile latch and a power supply node, the anti-fuse test circuit including a current supply arranged in series with a controllable impedance path.

8. The programmable latch circuit of claim 7, wherein:

the current supply comprises an IGFET that receives a bias voltage at its gate, the bias voltage varying between a high power supply level and a low power supply level.

9. A programmable latch circuit, comprising:

a volatile latch circuit comprising a pair of latch transistors cross-coupled between a first data node and a second data node and formed in an integrated circuit substrate;

at least one anti-fuse structure coupled to at least one of the data nodes; and

a self-test circuit formed in the integrated circuit substrate including a first self-test section coupled to at least one of the data nodes that includes a first current source circuit and a first switch device arranged in series, the first switch device providing a low impedance in a test mode and a high impedance in a non-test mode.

10. The programmable latch circuit of claim 9, wherein:

the at least one anti-fuse structure includes at least a first primary anti-fuse structure coupled to the first data node and at least a second primary anti-fuse structure coupled to the second data node; and

the self-test circuit further includes

the first self-test section coupled the first data node and the first switch device providing the low impedance in a first test mode, and

a second self-test circuit coupled to the second data node that includes a second current source circuit and a second switch device arranged in series, the second switch device providing a low impedance in a second test mode and a high impedance in the non-test mode.

11. The programmable latch circuit of claim 9, wherein:

the at least one anti-fuse structure includes

a first primary anti-fuse structure and a first redundant anti-fuse structure coupled to a first data node of the volatile latch circuit, and

a second primary anti-fuse structure and a second redundant anti-fuse structure coupled to a second data node of the volatile latch circuit.

12. The programmable latch circuit of claim 9, wherein:

the at least one anti-fuse structure includes at least a first primary anti-fuse structure coupled between the first data node and a high power supply node; and

the self-test circuit includes the first self-test section coupled between a second data node and the high power supply node, and the first switch device is a p-channel insulated gate field effect transistor.

13. The programmable latch circuit of claim 12, wherein:

the at least one anti-fuse structure further includes a second primary anti-fuse structure coupled between the second data node and the high power supply node; and

the self-test circuit further includes a second self-test section coupled between the first data node and the high power supply node that includes a second current source circuit and a second switch device arranged in series, the second switch device comprising a p-channel insulated gate field effect transistor that provides a low impedance in a test mode and a high impedance in a non-test mode.

14. The programmable latch circuit of claim 9, further including:

at least a first resistor formed in the integrated circuit substrate and coupled between the at least one anti-fuse structure and a first power supply node.

15. The programmable latch circuit of claim 9, further including:

the pair of latch transistors having sources coupled to a low power supply voltage and having a first threshold voltage; and

at least a first data path comprising

a first data program path coupled between the at least one anti-fuse structure and at least one data node that is enabled to program the first primary anti-fuse structure into a low impedance state, and

a first data load path coupled between the at least one anti-fuse structure and the at least one data node that is enabled to read a state of the first primary anti-fuse structure, the first data load path consisting of load transistors having a threshold voltage that is less than the first threshold voltage.

16. The programmable latch circuit of claim 15, wherein:

the load transistors are selected from the group consisting of p-channel insulated gate field effect transistors (IGFETs) and native n-channel IGFETs having threshold voltages with an absolute value no greater than 200 mV.

17. A method of programmable latching, comprising the steps of:

programming at least one anti-fuse device into a predetermined state by applying a programming voltage to a program path coupled to the anti-fuse device; and

loading a data value into a volatile latch circuit by enabling a data load path, different from the program path, coupled between the at least one anti-fuse device and the volatile latch circuit, the data value being determined by the state of the at least one anti-fuse device.

18. The method of programmable latching of claim 17, wherein:

enabling the data path includes enabling a plurality of p-channel insulated gate field transistors having source-drain paths that form at least a portion of the data path.

19. The method of programmable latching of claim 17, further including:

providing a resistor, formed in the same integrated circuit as the volatile latch circuit, between the at least one anti-fuse device and a programming power supply node; and

in a test mode, latching a data value in the volatile latch circuit based on a comparison between a current drawn by the at least one anti-fuse device and a current drawn by a current source circuit formed in the same substrate as the volatile latch circuit.

20. The method of programmable latching of claim 17, further including:

providing first and second anti-fuse devices in parallel between a first node of the volatile latch circuit and a programming voltage node;

providing third and fourth anti-fuse devices in parallel between a second node of the volatile latch circuit and the programming voltage node;

providing both a programming path and data load path between each anti-fuse device and the node of the volatile latch to which the anti-fuse device is coupled;

programming the second anti-fuse device if a programming of the first anti-fuse is not successful; and

programming the fourth anti-fuse device if a programming of the third anti-fuse is not successful.