Augmenting semiconductor's devices quality and reliability

• US 7,340,359 B2
• Filed: 01/31/2006
• Issued: 03/04/2008
• Est. Priority Date: 05/02/2005
• Status: Active Grant

• Current Assignee: Optimal Plus Ltd. (Emerson Electric Company)
• Original Assignee: Optimaltest, Ltd. (Emerson Electric Company)
• Inventors: Erez, Nir, Balog, Gil
• Primary Examiner(s): WACHSMAN, HAL D
• Application Number:
  US11/343,209
• Publication Number:
  US 20060267577A1
• Time in Patent Office: 763 Days
• Field of Search: 702/81, 702/82
• US Class Current: 702/81
• CPC Class Codes: G01R 31/287 Procedures; Software aspects
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors

Abstract

A method for augmenting quality or reliability of semiconductor units, including providing few populations of semiconductor units that are subject to quality or reliability testing. The populations include few quality or reliability fail candidate populations and other population(s). The method includes the step of associating test flows to the populations. Each test flow includes stress testing sequence. The stress testing sequence for the quality or reliability fail candidate population includes a stress test of increased duration compared to duration of a stress test in the test flow of the other population. The stress test sequence for the other population includes a stress test of increased voltage compared to corresponding operating voltage specification for a semiconductor unit. The method further includes the step of applying, within a sort testing stage, the corresponding test flow to the populations and identifying any unit which failed the stress sequence.

Claims

1. A method for augmenting quality or reliability of semiconductor units, comprising:

(a) providing at least two populations of semiconductor units that are subject to quality or reliability testing;

the at least two populations including at least one quality or reliability fail candidate population and at least one other population;

(b) associating test flows to the at least two populations;

each test flow including a stress testing sequence;

wherein the stress testing sequence for at least one of the quality or reliability fail candidate populations includes a stress test of increased duration as compared to a duration of a stress test in a test flow of at least one of the other populations;

wherein the stress testing sequence for at least one of the other populations includes a stress test of increased voltage as compared to a corresponding operating voltage specification for a semiconductor unit of the semiconductor units; and

(c) applying, within a sort testing stage, a corresponding test flow to each of the at least two populations and identifying any semiconductor unit which failed the stress testing sequence.

2. The method according to claim 1, wherein the semiconductor unit is a semiconductor device.

3. The method according to claim 2, wherein the semiconductor unit is a module within the semiconductor device.

4. The method according to claim 3, wherein the modules are at least one of a group that includes:

a micro-processor, DSP, Memory, I/O, Specialty ASIC, Control, Analog, and RF.

5. The method according to claim 3, wherein at least one of the quality or reliability fail candidate populations extends to at least one module in a semiconductor device in a wafer within a lot that is subjected to sort testing.

6. The method according to claim 3, wherein at least one of the quality or reliability fail candidate populations extends to at least one module in all semiconductor devices of at least one wafer within a lot that is subjected to sort testing.

7. The method according to claim 2, wherein at least one of the quality or reliability fail candidate populations extends to at least one semiconductor device in a wafer within a lot that is subjected to sort testing.

8. The method according to claim 2, wherein at least one of the quality or reliability fail candidate populations extends to all semiconductor devices of at least one wafer within a lot that is subjected to sort testing.

9. The method according to claim 2, wherein the semiconductor device is a memory device and wherein the stress test of increased duration has a larger number of test cycles to be applied to the semiconductor device as compared to a number of test cycles of a stress testing sequence of at least one of the other populations.

10. The method according to claim 9, wherein the memory device has memory modules, and wherein a memory module is selected from a group that includes:

at least one row of cells or portion thereof, at least one column of cells or portion thereof, and an array of cells defined by an intersection of at least two rows and at least two columns, and wherein the stress test of increased duration has a larger number of test cycles to be applied to at least one of the memory modules as compared to a number of test cycles of a stress testing sequence of at least one of the other populations.

11. The method according to claim 1, wherein the stress testing sequence for at least one of the quality or reliability fail candidate populations further includes, a stress test with an increased voltage as compared to a corresponding operating voltage specification for a semiconductor unit of the semiconductor units.

12. The method according to claim 1, wherein the stress testing sequence for at least one of the quality or reliability fail candidate populations further includes, a stress test operable under a different temperature as compared to a corresponding operating temperature specification for a semiconductor unit of the semiconductor units.

13. The method according to claim 1, wherein the stress testing sequence for at least one of the quality or reliability fail candidate populations further includes, a stress test operable under a different frequency as compared to a corresponding operating frequency specification for a semiconductor unit of the semiconductor units.

14. The method according to claim 1, wherein the associating test flows further includes, associating at least one test flow that includes a post-stress sequence with respect to at least one of the quality or reliability fail candidate populations;

and wherein the applying, within a sort testing stage, further includes, at least one test flow that has the stress testing sequence and post-stress testing sequence with respect to at least one of the quality or reliability fail candidate populations for identifying any semiconductor unit which failed the post-stress testing sequence.

15. The method according to claim 1, wherein the associating test flows further includes, associating at least one test flow containing identical pre-stress and post-stress testing sequences with respect to at least one of the quality or reliability fail candidate populations;

and wherein the applying within a sort testing stage, further includes, at least one test flow that includes a pre-stress testing sequence, stress testing sequence and post-stress testing sequence with respect to at least one of the quality or reliability fail candidate population for further identifying any semiconductor unit which failed the post-stress testing sequence.

16. The method according to claim 1, wherein at least one of the stress testing sequences is updated dynamically within a sort testing stage.

17. The method according to claim 16, wherein at least one of the quality or reliability fail candidate populations is updated dynamically.

18. The method according to claim 17, wherein the dynamic update is based on data fed forward from historical information.

19. The method according to claim 18, wherein the historical information includes previously gathered and processed data of at least one of shifts or failure signatures in wafer Fab parametric E-Test.

20. The method according to claim 19, further comprising:

backward analyzing data processed in the sort testing stage, and in response thereto, dynamically updating the at least one of the quality or reliability fail candidate populations.

21. The method according to claim 20 wherein the backward analyzing includes identifying at least one outlier unit and including the at least one outlier unit in at least one quality or reliability fail candidate population.

22. The method according to claim 21, further comprising associating a modified test flow to a quality or reliability fail candidate population that includes the at least one outlier unit, and applying, within the sort testing stage, the modified test flow sequence to at least one of the quality or reliability fail candidate populations for identifying at least one outlier unit which failed the test.

23. The method according to claim 18, wherein the historical information includes previously gathered and processed data of shifts or failure signatures in wafer Fab Particle signatures.

24. The method according to claim 18, wherein the historical information includes previously gathered and processed data of shifts or failure signatures in a given socket repair at a given stage.

25. The method according to claim 18, wherein the historical information includes previously gathered and processed data of semiconductor units with high redundancy repair features built-in.

26. The method according to claim 18, wherein the historical information included previously gathered and processed data of a shift in a process window parameter can go out of statistical control.

27. The method according to claim 1, wherein the stress testing sequence for at least one of the other population is updated dynamically within the sort testing stage.

28. A method for augmenting quality or reliability of semiconductor units, comprising:

(a) providing at least two populations of semiconductor units that are subject to quality or reliability testing;

(b) associating test flows that include stress testing sequences to the at least two populations;

a first flow from the test flows further including an identical first pre-stress testing sequence and first post-stress testing sequence;

a second flow from the test flows further including an identical second pre-stress testing sequence and a second post-stress testing sequence;

the first and the second stress testing sequences being different; and

(c) applying, within a sort testing stage;

the test flow that included the first pre-stress testing sequence, the stress testing sequence, and the first post-stress testing sequence, to at least one of the at least two populations; and

the test flow that included the second pre-stress testing sequence, the stress testing sequence, and the second post-stress testing sequence, to at least one other of the at least two populations;

for identifying any semiconductor unit which failed the first or second post-stress testing sequence.

29. The method according to claim 28, wherein the first and second flows are identical.

30. The method according to claim 28, wherein at least two stress testing sequences for the at least two populations are different.

31. The method according to claim 28, wherein the first flow further includes an additional pre-stress testing sequence and an additional post-stress testing sequence.

32. A method for augmenting quality or reliability of semiconductor units, comprising:

(a) providing at least two populations of semiconductor units that are subject to quality or reliability testing;

the at least two populations including at least one quality or reliability fail candidate population and at least one other population;

(b) associating test flows to the at least two populations;

each test flow including a stress testing sequence;

the stress testing sequence for at least one of the quality or reliability fail candidate populations including a stress test of increased duration as compared to a duration of a stress test in a test flow of a population of at least one of the other populations;

wherein the stress testing sequence for at least one of the other populations includes a stress test of increased voltage as compared to a corresponding operating voltage specification for the semiconductor unit;

(c) applying, within a final testing stage, a corresponding test flow to each of the at least two populations and identifying any semiconductor unit which failed the stress testing sequence.

33. A method for providing augmented quality or reliability tests configured to be applied to semiconductor units during a testing stage, comprising:

(a) analyzing data gathered from historical information that pertains to semiconductor units for identifying at least two populations of semiconductor units that are subject to quality or reliability testing;

the at least two populations including at least one quality or reliability fail candidate population and at least one other population;

wherein at least one of the quality or reliability fail candidate populations includes a geographical area in a wafer that includes a cluster of at least two consecutive devices, such that any device in the cluster has at least one neighboring device which also belongs to the cluster; and

providing at least two different test flows and associating at least one of the at least two different test flows to one of the quality or reliability fail candidate populations, and at least one other test flow of the at least test flows to at least one of the other population;

wherein the at least two different test flows are configured to be applied, within a testing stage, to the associated populations for identifying a semiconductor unit which has failed the test.

34. The method according to claim 33, wherein the geographical area in the wafer is in a form of a member in a group that includes a ring, slice, doughnut, and i o'"'"'clock where 1<

i<

12.

35. The method according to claim 33, wherein the method is performed at a sort stage.

36. The method according to claim 33, wherein the method is performed at a final stage.

42. The method according to claim 36, wherein the repertoire of test flows includes a stress test with increased voltage as compared to a corresponding operating voltage specification for a semiconductor unit of the semiconductor units.

37. A method for providing augmented quality or reliability tests configured to be applied to semiconductor units during a testing stage, comprising:

(a) analyzing data gathered from historical information that pertain to semiconductor units for identifying at least two populations of semiconductor units that are subject to quality or reliability testing;

the at least two populations including at least one quality or reliability fail candidate population and at least one other population;

at least one of the quality or reliability fail candidate populations including semiconductor units with the same lithography exposure; and

(b) providing at least two different test flows and associating at least one of the at least two different test flows to one of the quality or reliability fail candidate populations, and at least one other test flow of the at least test flows to at least one of the other population;

wherein the at least two different test flows are configured to be applied, within a testing stage, to the associated populations, for identifying a semiconductor unit which has failed the test.

38. The method according to claim 37, wherein the method is performed at a sort stage.

39. The method according to claim 37, wherein the method is performed at a final stage.

40. A method for providing augmented quality or reliability tests configured to be applied to semiconductor units during a testing stage, comprising:

(a) analyzing data gathered from historical information that pertain to semiconductor units for identifying at least two populations of semiconductor units that are subject to quality or reliability testing;

the at least two populations including at least one quality or reliability fail candidate population and at least one other population;

at least one of the quality or reliability fail candidate populations including semiconductor units with a same relative location across lithography exposures; and

(b) providing at least two different test flows and associating at least one of the at least two different test flows to at least one of the quality or reliability fail candidate populations, and associating at least one of an other different test flow to at least one of the other populations, the at least two different test flows being configured to be applied, within a testing stage, to associated populations for identifying a failed semiconductor unit.

41. The method according to claim 40, wherein the method is performed at a sort stage.

43. The method according to claim 40, wherein the method is performed at a final stage.

44. A method for providing augmented quality or reliability tests configured to be applied to semiconductor units during a manufacturing stage, comprising:

(a) analyzing data gathered from historical information that pertains to semiconductor units for identifying at least two populations of semiconductor units that are subject to quality or reliability testing;

the at least two populations including at least one quality or reliability fail candidate population and at least one other population;

(b) providing a repertoire of test flows;

(c) for at least one of the quality or reliability fail candidate populations performing the following, including;

i) providing a reference burn-in units fail score in respect to the quality or reliability fail candidate population of a semiconductor sample;

ii) selecting a test flow from the repertoire of test flows;

iii) applying the selected test flow to the semiconductor sample of the quality or reliability fail candidate population and logging the tested unit'"'"'s-fail score;

the semiconductor sample being substantially identical to the semiconductor sample of (c) and (i);

iv) applying a burn-in test to the quality or reliability fail candidate population of the semiconductor sample of (iii) and logging the tested burn-in units fail score;

wherein units having failed in the tested units fail score are excluded from the burn-in units fail score;

v) repeating at least once (ii) to (iv), in respect to different test flow from the repertoire of test flows;

vi) determining a prevailing test flow from among the test flows used in (ii), (iii) and (iv), according to a decision criterion;

wherein the decision criterion is dependent at least on the reference burn-in units fail score, and the tested units fail score and tested burn-in units fail score of the prevailing test flow; and

associating the prevailing test flow to the quality or reliability fail candidate population, for applying to semiconductor units during a manufacturing stage.

45. The method according to claim 44, wherein the decision criterion stipulates that the tested burn-in units fail score of the prevailing test flow is lowest as compared to the burn-in units fail scores of the other test flows used in (ii), (iii) and (iv) and that the tested burn-in units fail score is lower than the reference burn-in units fail score.

46. The method according to claim 44, wherein the semiconductor sample is at least one wafer of a lot and the substantially identical semiconductor sample is at least one other wafer from the lot.

47. The method according to claim 44, wherein the repertoire of test flows includes a stress test of increased duration as compared to a duration of a stress test in the test flow of at least one of the other populations.

48. The method according to claim 47, wherein the semiconductor device is a memory device and wherein the stress test of increased duration consists of a larger number of test cycles to be applied to the semiconductor device as compared to a number of test cycles of a stress test for the at least one other population.

49. The method according to claim 44, wherein the repertoire of test flows includes a stress test operable under a different temperature as compared to a corresponding operating temperature specification for a semiconductor unit of the semiconductor units.

50. The method according to claim 44, wherein the repertoire of test flows includes a stress test operable under a different frequency as compared to a corresponding operating frequency specification for a semiconductor unit of the semiconductor units.

51. A method for providing augmented quality or reliability tests configured to be applied to semiconductor units during sort stage, comprising:

(a) analyzing data gathered from historical information that pertains to semiconductor units for identifying at least one populations of semiconductor units that is subject to quality or reliability testing;

(b) associating a respective selected test flow to each one of the at least one populations according to a decision criterion that includes a condition that a fail rate of units in a burn-in test that follows the selected test flow is lower than a fail rate of units in a burn-in test that follows a non-selected test flow.

52. A system for augmenting quality or reliability of semiconductor units, comprising:

means including a processor and storage configured to provide at least two populations of semiconductor units that are subject to quality or reliability testing;

the at least two populations including at least one quality or reliability fail candidate population and at least one other population;

means including a processor and storage configured to associate test flows to the at least two populations;

each test flow including a stress testing sequence;

wherein the stress testing sequence for at least one of said the quality or reliability fail candidate populations includes a stress test of increased duration as compared to a duration of a stress test in the test flow of at least one of the other populations;

wherein the stress testing sequence for at least one of the other populations includes a stress test of increased voltage as compared to a corresponding operating voltage specification for a semiconductor unit of the semiconductor units; and

means configured to apply, within a testing stage, the corresponding test flow to each population and identifying any semiconductor unit which failed the stress testing sequence.

53. The system according to claim 52, wherein the testing stage is within a sort stage.

54. The system according to claim 52, wherein the testing stage is within a final stage.

55. The system according to claim 52, wherein said means including a processor and storage further includes, a data manager coupled to a plurality of data storages, and wherein the means configured to apply further includes, a station controller associated with the plurality of data storages, wherein the station controller is associated with handling equipment and with automatic test equipment.

56. A system for augmenting quality or reliability of semiconductor units, comprising:

means including a processor and storage configured to provide at least two populations of semiconductor units that are subject to quality or reliability testing;

means including a processor and storage configured to associate test flows that include stress testing sequences to the at least two populations;

a first test flow from among the test flows further including an identical first pre-stress testing sequence and first post-stress testing sequence;

a second test flow from the test flows further including an identical second pre-stress testing sequence and second post-stress testing sequence;

wherein the first and second stress testing sequences are different; and

means configured to apply, within a testing stage, a test flow that includes the first pre-stress testing sequence, the first stress testing sequence and the first post-stress testing sequence, and a test flow that includes the second pre-stress testing sequence, the second stress testing sequence and the second post-stress testing sequence, to at least one of the at least two populations for identifying any semiconductor unit which failed the first or second post-stress testing sequence.

57. The system according to claim 56, wherein the testing stage is within a sort stage.

58. The system according to claim 56, wherein the testing stage within a final stage.

59. The system according to claim 56, wherein the means including a processor and storage further includes, a data manager coupled to a plurality of data storages, and wherein the means configured for applying further includes, a station controller associated with the plurality of data storages, wherein the station controller is associated with handling equipment and with automatic test equipment.

60. A computer program product containing a computer readable medium having instructions encoded therein for operation of a computing device, comprising:

instructions for performing at least one of storing or reading storage data indicative of at least two populations of semiconductor units that are subject to quality or reliability testing, wherein the at least two populations include at least one quality or reliability fail candidate population and at least one other population;

instructions for performing at least one of storing or reading test flow information associated with the at least two populations of semiconductor units, wherein the test flow information contains a stress testing sequence, wherein the test stressing sequence for at least one of the quality or reliability fail candidate populations includes a stress test of increased duration as compared to a duration of a stress test in one of the other populations, the stress testing sequence for at least one of the other population including a stress test of increased voltage as compared to a corresponding operating voltage specification for a semiconductor unit of the semiconductor units; and

instructions for applying within a testing stage, an association of a corresponding test flow to each of the at least two populations, to enable an identification of a failing semiconductor unit.

61. A computer program product containing a computer readable medium having instructions encoded therein for operation of a computing device, comprising:

instructions for performing at least one of storing or reading storage data indicative of at least two populations of semiconductor units that are subject to quality or reliability testing, wherein the at least two populations include at least one quality or reliability fail candidate population and at least one other population;

instructions for performing at least one of storing or reading test flow data associated with the at least two populations of semiconductor units, wherein the test flow data includes stress test sequences to the at least two populations, wherein a first test flow from the test flow data includes an identical first pre-stress test sequence and a first post-stress test sequence, and a second test flow from the test flow data includes a second pre-stress test sequence and a second post-stress test sequence, the sequences of the first and second test flow data being different; and

instructions to apply, within a testing stage, test flow that include a pre-stress test sequence, an associated stress test sequence, and a post-stress test sequence to at least one of an associated population, to enable an identification of a semiconductor unit that failed the post-stress test sequence.