Weighted event counting system and method for processor performance measurements

• US 7,340,378 B1
• Filed: 11/30/2006
• Issued: 03/04/2008
• Est. Priority Date: 11/30/2006
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Floyd, Michael S., Rawson, Freeman Leigh III, Ghiasi, Soraya, Rajamani, Karthick, Keller, Thomas W. Jr., Rubio, Juan C.
• Primary Examiner(s): Raymond; Edward
• Application Number:
  US11/565,106
• Time in Patent Office: 460 Days
• Field of Search: 702/186, 702182-185, 702/188, 709/238, 709/242, 709/201, 714/25, 714/48
• US Class Current: 702/186
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware
• CPC Class Codes: G06F 2201/86 Event-based monitoring
• CPC Class Codes: G06F 2201/88 Monitoring involving counting

Abstract

A weighted event counting system and method for processor performance measurements provides low latency and low error performance measurement capability. A weighted performance counter accumulates a performance count according to a plurality of event signals provided from functional units in the processor. Differing weights are applied to the event signals in according to the correlation between each event with processor performance. The weights may be provided from programmable registers, so that the weights can be adjusted under program control. The event signals may be combined to reduce the bit-width of the set of event signal, with mutually-exclusive events merged in single fields of the combinatorial result and events having the same weights merged according to a sub-total. The weights are applied to the combinatorial result and used to update a performance count. The performance count can then be used by power management software or hardware to make adjustments in operating parameters of the processor.

Claims

1. A method of determining a performance level of a processor, comprising:

receiving a plurality of event signals from functional units within said processor corresponding to differing events within said processor;

updating a performance counter in conformity with a totality of said plurality of event signals, wherein said updating assigns differing weights to at least two of said plurality of event signals, whereby a latency between accumulation of performance metrics corresponding to said events is reduced and said events are further separately weighted according to their correlation to performance of said processor; and

reading said performance counter at periodic intervals to obtain a performance count.

2. The method of claim 1, wherein said receiving and updating are performed at each clock cycle of said processor.

3. The method of claim 1, further comprising adjusting said weights in conformity with values input to said processor.

4. The method of claim 1, further comprising:

encoding said plurality of received event signals to provide a combinatorial value; and

applying said weights to said combinatorial value to provide an update value, and wherein said updating adds said update value to a present value of said performance count to obtain a next performance count.

5. The method of claim 1, wherein said encoding merges said events that correspond to equal ones of said weights.

6. The method of claim 1, wherein said encoding encodes mutually exclusive events according to codes within a field of said combinatorial value.

7. The method of claim 1, further comprising:

determining a power management figure for said processor in conformity with said performance count; and

adjusting an operating parameter of said processor in conformity with a result of said determining.