Addressing scheme supporting fixed local addressing and variable global addressing

• US 7,340,546 B2
• Filed: 05/15/2003
• Issued: 03/04/2008
• Est. Priority Date: 05/15/2002
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rowlands, Joseph B., Moll, Laurent R.
• Primary Examiner(s): Kindred; Alford
• Assistant Examiner(s): VIDWAN, JASJIT S
• Application Number:
  US10/439,343
• Publication Number:
  US 20030233495A1
• Time in Patent Office: 1,755 Days
• Field of Search: None
• US Class Current: 710/220
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 12/082 Associative directories G06F12/0822 takes precedence
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 2212/1048 Scalability
• CPC Class Codes: G06F 2212/2542 Non-uniform memory access [NUMA] architecture
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions

Abstract

A node comprises one or more resources and a register programmable with an indication during use. The one or more resources are addressed with addresses within a local region of an address space. The indication identifies a second region of the address space that is aliased to the local region, and other nodes address the one or more resources using addresses in the second region.

Claims

1. A node comprising:

locations within the node in which the locations are addressed with addresses associated with a local region of the node and also addressed with addresses associated with a separate second region of the node that is aliased with the local region, in which a selected number of lower significant bits of the addresses associated with the locations in the local region to a respective same lower significant bits of the addresses associated with the locations in the second region; and

a register programmable to store a value during use to configure the node, wherein the node is identified by a set of most significant bits of the addresses associated with the second region to indicate that the second region is aliased with the local region, and wherein the second region has global addressing for internode access;

wherein when an agent in the node performs an access to a particular global address in the second region, respective aliased location in the local region is accessed and if the respective aliased location in the local region corresponds to an input/output or interface device within the node or corresponds to a memory location that does not require coherency, the access is performed locally through the local region, but if the respective aliased location in the local region corresponds to a memory location requiring coherency, the access is performed through the second region by generating a global coherent transaction through the second region, and wherein an access from another node to access the particular global address in the second region is performed locally through the respective aliased location if an agent of the another node has ownership of the respective aliased location in the local region, but if the agent of the another node does not have ownership of the respective aliased location, a global coherent transaction is generated to access the particular global address, in which accesses through the local region and through the second region use the same respective lower significant bits of an address to access the locations in the local region and the second region.

2. The node as recited in claim 1 wherein an access to the particular global address by the agent in the node that requires only intranode coherency, not internode coherency, is obtained through aliased location of the local region.

3. The node as recited in claim 1 wherein a memory is coupled to the node to provide memory locations for the node.

4. A method comprising:

assigning a first address for a location in a node, in which the first address is associated with a local region of the node;

assigning a second address to a location, in which the second address is associated with a separate second region of the node that is aliased with the local region, in which a selected number of lower significant bits of the address associated with the location in the local region to a respective same lower significant bits of the address associated with the location in the second region;

assigning an identity for the node by loading a value in a register, in which the node is configured by a set of most significant bits of the addresses associated with the second region to indicate that the second region is aliased with the local region, and wherein the second region has global addressing for internode access;

performing a global access to the second address by an agent within the node, in which a respective aliased location in the local region is accessed and if the respective aliased location in the local region corresponds to an input/output or interface device within the node or corresponds to a memory location that does not require coherency, performing the access locally through the local region;

performing the access by generating a global coherent transaction through the second region if the respective aliased location corresponds to a memory location requiring coherency; and

having another node access the second address of the second region and to perform the access through the respective aliased location of the local region if an agent of the another node has ownership of the respective aliased location, but if the agent of the another node does not have ownership of the respective aliased location, a global coherent transaction is generated to access the second address, in which the accesses through the local region and through the second region use the same respective lower significant bits of an address to access a particular resource.

5. The method as recited in claim 4 further comprising accessing the second address by the agent in the node that requires only intranode coherency, not internode coherency, in which the access is obtained through the respective aliased location in the local region.

6. The method as recited in claim 4 further comprising obtaining a shared access from the another node only through the second region.

7. The method as recited in claim 4 further including assigning respective addresses to various resources of the node.