Cache for instruction set architecture

• US 7,340,562 B2
• Filed: 07/24/2003
• Issued: 03/04/2008
• Est. Priority Date: 10/28/2002
• Status: Expired due to Term

• Current Assignee: QST Holdings LLC
• Original Assignee: NVIDIA Corporation
• Inventors: Ramchandran, Amit
• Primary Examiner(s): Bragdon, Reginald
• Assistant Examiner(s): Flournoy, Horace L.
• Application Number:
  US10/628,036
• Publication Number:
  US 20040093465A1
• Time in Patent Office: 1,685 Days
• Field of Search: 711/131
• US Class Current: 711/108
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/287 Multiplexed DMA G06F13/30 takes precedence
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A distributed data cache includes a number of cache memory units or register files each having a number of cache lines. Data buses are connected with the cache memory units. Each data bus is connected with a different cache line from each cache memory unit. A number of data address generators are connected with a memory unit and the data buses. The data address generators retrieve data values from the memory unit and communicate the data values to the data buses without latency. The data address generators are adapted to simultaneously communicate each of the data values to a different data bus without latency. The cache memory units are adapted to simultaneously load data values from the data buses, with each data value loaded into a different cache line without latency.

Claims

1. A distributed data cache coupled to one of a plurality of reconfigurable execution nodes (RXN), wherein the reconfigurable execution nodes are coupled by a programmable interconnection network having a network root and a plurality of crosspoint switches, each of the RXNs being selectively configurable to perform a one of a plurality of processing operations, the distributed data cache comprising:

a plurality of cache memory units each having a plurality of cache ports;

a plurality of data buses connected with each of the cache memory units, wherein each of the plurality of data buses is connected with one of the plurality of cache ports of each of the cache memory units;

the reconfigurable execution node adapted for actively processing data and having at least one data input and at least one data output, wherein the data input and data output are connected with the plurality of data buses; and

wherein the RXN is adapted to be reconfigured to perform a sequence of operations to actively process data responsive to a sequence of the control words stored in the cache memory.

2. The distributed data cache of claim 1, further comprising a multiplexer for alternately connecting the data input with each of the plurality of data buses.

3. The distributed data cache of claim 1, further comprising a multiplexer for alternately connecting the data ouput with each of the plurality of data buses.

4. The distributed data cache of claim 1, further comprising a plurality of data address generators connected with a memory unit and the plurality of data buses.

5. The distributed data cache of claim 4, wherein the plurality of data address generators are adapted to retrieve a plurality of data values from the memory unit and communicate the plurality of data values to the plurality of data buses.

6. The distributed data cache of claim 5, wherein the plurality of data address generators are adapted to simultaneously communicate the plurality of data values to the plurality of data buses, wherein each of the plurality of data value is communicated to a different one of the plurality of data buses.

7. The distributed data cache of claim 6, wherein the first cache memory unit is adapted to simultaneously load a plurality of data values from the plurality of data buses, such that each of the plurality of data values is loaded in a different one of the plurality of cache lines of the first cache memory unit through the same port.

8. The distributed data cache of claim 1, wherein the number of cache lines of the first cache memory unit are equal to the number of data buses.

9. The distributed data cache of claim 1, further comprising at least one additional cache memory unit also having a plurality of cache lines, wherein each cache line of the additional cache memory unit is connected with the plurality of data buses.

10. The distributed data cache of claim 9, wherein the total number of cache memory units is equal to the number of cache lines in each cache memory unit.

11. The distributed data cache of claim 1, wherein the RXN includes a plurality of selectively configurable elements each having a configuration determined by the value of a multi-bit control word, the bits being simultaneously supplied in one or more of the control words stored in the cache memory units over the data buses.

12. The distributed data cache of claim 11, wherein each of the memory units comprises a plurality of cache lines, each cache line being associated with one of the plurality of cache ports, each cache line storing one of the control words, the sequence of control words being retrieved by an index uniquely identifying the cache line, a sequence of the indexes defining a single access control word.

13. The distributed data cache of claim 12, wherein the access control world is identified by a flag bit, the remainder of the access control word comprising a sequence of indexes.

14. An apparatus for transferring a plurality of data values arranged in a matrix, the apparatus coupled to one of a plurality of heterogeneous processing nodes, wherein the heterogeneous processing nodes are coupled by a programmable interconnection network having a network root and a plurality of crosspoint switches, the apparatus comprising:

a plurality of cache memory units, each cache memory unit having a plurality of cache ports; and

a plurality of data buses, each data bus connected with a different one of the plurality of cache ports from each of the cache memory or register file units so that each of the data buses is connected to one port of every one of the data buses.

15. The apparatus of claim 14, further comprising a plurality of data address generators adapted to retrieve a plurality of sets data values from the memory unit and communicate the plurality of sets data values to the plurality of data buses, the apparatus being configured to transpose a matrix stored in the main memory by reading a matrix comprising a plurality of row elements from the main memory into the plurality of data buses, then simultaneously transferring the row elements to the cache ports of each one of the cache memories, and repeating the operation for each row of the stored matrix.

16. The apparatus of claim 14, wherein the plurality of data address generators are adapted to sequentially communicate the plurality of sets of data values with the plurality of data buses;

and

wherein each and every of the cache memory units is adapted to simultaneously load one of the sets of data values from the plurality of data buses, such that each data value of the set of data values is simultaneously loaded in a different one of the plurality of cache orts of the cache memory unit or register file.

17. A method for transferring a plurality of data values arranged in a matrix to transpose the matrix, the matrix including a plurality of heterogeneous processing nodes coupled by a programmable interconnection network having a network root and a plurality of crosspoint switches, the method comprising:

retrieving a first subset of data values from the plurality of data values from a memory unit storing the matrix in rows;

simultaneously transferring the first subset of data values comprising one of the rows of the matrix;

to a plurality of data buses, wherein each data value of the first subset is transferred to a different one of the plurality of data buses;

simultaneously loading the first subset of data values from the plurality of data buses to a first cache memory unit having a plurality of cache ports, wherein each cache port receives a data value from a different one of the plurality of data buses to define a column of the matrix; and

repeating the operation for each row of the matrix to complete transposing of the matrix.