Bios-level incident response system and method

• US 7,340,594 B2
• Filed: 06/30/2004
• Issued: 03/04/2008
• Est. Priority Date: 06/30/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: First, Carl L., Jones, Morris E.
• Primary Examiner(s): Trujillo; James K.
• Assistant Examiner(s): Brown; Michael J
• Application Number:
  US10/882,056
• Publication Number:
  US 20060005004A1
• Time in Patent Office: 1,343 Days
• Field of Search: 713/2
• US Class Current: 713/2
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1441 Resetting or repowering

Abstract

A system, apparatus, and method for depicting and responding to systematic problems and/or incidents in computing devices at a Basic Input/Output System level are described herein.

Claims

1. A computing device, comprising:

a processor;

an operating system operated by the processor; and

a BIOS operated by the processor, the BIOS containing executable instructions, and adapted to;

check a BIOS-accessible incident flag independent of the operating system, when executed; and

if said incident flag indicates an incident, respond to said incident independent of the operating system, wherein said response includes depiction of an incident relevant message retrieved from a BIOS-accessible memory.

2. The computing device of claim 1, further comprising the BIOS being adapted to check a boot continuation flag, and stop a boot process if said boot continuation flag indicates a boot stopping incident.

3. The computing device of claim 1, wherein at least some of said executable instructions are stored in a BIOS-accessible memory.

4. The computing device of claim 1, wherein said executable instructions are adapted to designate a memory of a separate computing device component for said incident flag.

5. The computing device of claim 1, wherein said executable instructions are adapted to provide corrective action appropriate to said incident.

6. The computing device of claim 1, further comprising a BIOS-accessible memory residing on a separate computing device component.

7. The computing device of claim 6, wherein at least some of said executable instructions reside on said BIOS-accessible memory of said separate computing device component.

8. The computing device of claim 6, wherein the separate computing device component is a bus-mastering device.

9. The computing device of claim 8, wherein at least some of said executable instructions reside in a memory of a networking component.

10. The computing device of claim 9, wherein the networking component is responsive to a wake-up signal to initiate a boot sequence on the computing device.

11. A computing device, comprising:

a processor;

a bus coupled to said processor;

a bus mastering component having a component memory and coupled to said bus; and

a BIOS containing executable instructions, and coupled to said bus, the execution instructions being adapted to;

detect, independent of an operating system, a BIOS-accessible incident flat;

obtain autonomic incident data from said component memory; and

respond to the obtained incident data during a boot sequence of the computing device, wherein said response includes depiction of an incident relevant message retrieved from the BIOS-accessible memory.

12. The computing device of claim 11, wherein the incident data comprises a component'"'"'s usage data.

13. The computing device of claim 12, wherein said component memory further comprises at least one predetermined response to incident data.

14. The computing device of claim 13, wherein said at least one predetermined response comprises a message.

15. A method of responding to an autonomic incident in a computing device, the method comprising:

setting an incident boot flag in a BIOS-accessible location;

storing autonomic incident response data in a BIOS-accessible memory;

identifying, independent of an operating system, said incident boot flag during a boot sequence of the computing device; and

responding to said autonomic incident during a boot sequence of the computing device with said autonomic incident response data from said BIOS-accessible memory, wherein said responding comprises depicting said autonomic incident response data as human readable desplayed text.

16. The method of claim 15, wherein said responding comprises depicting audibly said incident response data.

17. The method of claim 15, wherein said identifying comprises comparing a predetermined incident identifier with a predetermined incident response identifier.

18. The method of claim 15, wherein said incident response data includes executable instructions for responding to said autonomic incident.

19. The method of claim 15, wherein said autonomic incident is a detection of a malicious program.

20. The method of claim 15, wherein said autonomic incident is a software update incident.

21. A computer-readable medium containing computer-executable instructions for responding to an autonomic incident in a computing device by:

setting an autonomic incident flag in a BIOS-accessible location storing autonomic incident response data including human readable response information in a BIOS-accessible memory;

identifying the autonomic incident independent of an operating system; and

responding to said autonomic response during a boot sequence of the computing device, wherein said responding comprises depicting said incident response data as human readable displayed text.

22. The computer-readable medium of claim 21, wherein said incident response data includes executable instructions for responding to said autonomic incident.

23. A system comprising:

a processor;

a bus coupled to said processor;

a disk drive coupled to said processor; and

a memory containing computer executable instructions, which when executed are operative to respond to an autonomic incident in a computing device by;

setting an autonomic incident flag in a BIOS-accessible location storing autonomic incident response data including human readable response information in a BIOS-accessible memory;

identifying the autonomic incident independent of an operating system; and

responding to said autonomic response during a boot sequence of the computing device, wherein said responding comprises depicting said incident response data as human readable displayed text.

24. The system of claim 23, wherein said incident response data includes executable instructions for responding to said autonomic incident.