Masking structure having multiple layers including amorphous carbon layer
First Claim
Patent Images
1. A memory device comprising:
- a substrate having a plurality of doped regions;
device structure formed over the substrate, the device structure including a plurality of gate structures, a plurality of contacts, each of the contacts being located between two gate structure and contacting one of the doped regions, and an insulating layer formed over the gate structures and the contacts; and
a masking structure formed over the substrate, the masking structure including an amorphous carbon layer and a cap layer, wherein the cap layer includes non-oxide materials.
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Abstract
A masking structure having multiple layers is formed. The masking structure includes an amorphous carbon layer and a cap layer formed over the amorphous carbon layer. The amorphous carbon layer includes transparent amorphous carbon. The cap layer includes non-oxide materials. The masking structure may be used as a mask in an etching process during fabrication of semiconductor devices.
104 Citations
58 Claims
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1. A memory device comprising:
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a substrate having a plurality of doped regions; device structure formed over the substrate, the device structure including a plurality of gate structures, a plurality of contacts, each of the contacts being located between two gate structure and contacting one of the doped regions, and an insulating layer formed over the gate structures and the contacts; and a masking structure formed over the substrate, the masking structure including an amorphous carbon layer and a cap layer, wherein the cap layer includes non-oxide materials. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A memory device comprising:
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a substrate having at least one alignment mark, and a plurality of doped regions; a plurality of gate structures over the substrate; an insulating layer over the gate structures; a plurality of contacts, each of the contacts being located between two gate structures, each of the contacts extending through the insulating layer and contacting one of the doped regions; an amorphous carbon layer over the substrate, wherein the amorphous carbon layer is transparent in visible light range for improving a reading of the alignment mark; and a cap layer over the amorphous carbon layer, wherein the cap layer includes non-oxide materials. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A memory device comprising:
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a substrate having a plurality of doped regions; a plurality of gate structures over the substrate; a glass layer over the gate structures; a barrier layer between the gate structures and the glass layer for preventing cross-diffusion between the gate structures and the glass layer; a plurality of contacts, each of the contacts being located between two gate structures and contacting one of the doped regions; an amorphous carbon layer over the substrate, wherein the amorphous carbon layer is transparent to radiation having wavelengths between 400 nanometers and 700 nanometers; and a cap layer formed directly over the amorphous carbon layer, wherein the cap layer includes non-oxide materials. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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40. A method comprising:
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forming a plurality of doped regions in a substrate of a memory device, the substrate including at least one alignment mark; forming a plurality of gate structures over the substrate; forming an insulating layer over the gate structures; forming a plurality of contacts, each of the contacts being located between two gate structures, each of the contacts extending through the insulating layer and contacting one of the doped regions; forming an amorphous carbon layer over the substrate, wherein the amorphous carbon layer is transparent in visible light range for improving a reading of the alignment mark; and forming a cap layer over the amorphous carbon layer, wherein the cap layer includes non-oxide materials. - View Dependent Claims (41, 42, 43, 44, 45, 46, 47, 48, 49, 50)
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51. A method comprising:
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forming a plurality of doped regions in a substrate of a memory device; forming a plurality of gate structures over the substrate; forming a glass layer over the gate structures; forming a barrier layer between the gate structures and the glass layer for preventing cross-diffusion between the gate structures and the glass layer; forming a plurality of contacts, each of the contacts being located between two gate structures and contacting one of the doped regions; forming an amorphous carbon layer over the substrate, wherein the amorphous carbon layer is transparent in visible light range; and forming a cap layer over the amorphous carbon layer, wherein the cap layer includes non-oxide materials. - View Dependent Claims (52, 53, 54, 55, 56, 57, 58)
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Specification