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Apparatus for reducing power supply noise in an integrated circuit

  • US 7,342,405 B2
  • Filed: 01/30/2002
  • Issued: 03/11/2008
  • Est. Priority Date: 01/18/2000
  • Status: Expired due to Term
First Claim
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1. For use in a semiconductor test system, a method for reducing variation in a voltage supplied to a power input terminal of a semiconductor device under test, said method comprising:

  • providing power through a probe card to said power input terminal of said semiconductor device under test;

    sensing a temporary change in current drawn by said input terminal of said semiconductor device; and

    providing supplemental current to said input terminal in response to said temporary change in current, said supplemental current compensating for said temporary change in current.

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