Revenue meter with power quality features

• US 7,342,507 B2
• Filed: 08/22/2005
• Issued: 03/11/2008
• Est. Priority Date: 08/09/1999
• Status: Expired due to Term

• Current Assignee: Power Measurement Ltd. (Schneider Electric SE)
• Original Assignee: Power Measurement Ltd. (Schneider Electric SE)
• Inventors: Teachman, Michael E., Jonker, Rene T., Antoniou, Constantine A., Gunn, Colin N., Przydatek, Piotr B.
• Primary Examiner(s): Hofsass; Jeffery
• Assistant Examiner(s): Yacob; Sisay
• Application Number:
  US11/208,926
• Publication Number:
  US 20060066456A1
• Time in Patent Office: 932 Days
• Field of Search: 340/870.02, 340/870.39, 340/521, 340/584, 340/632, 340/310.11, 340/538.17, 340/605, 379/106.07, 379 8819- 8821, 379/37, 324/74, 324/76, 324/14, 324/156, 324/157, 702/61
• US Class Current: 340/870.02
• CPC Class Codes: G01R 21/133 by using digital technique

Abstract

Power quality detection, monitoring, reporting, recording and communication in a revenue accuracy electrical power meter is disclosed. Transient events are detected by monitoring the wave shape of the electrical power and comparing deviations to a known threshold. Sags and Swells are detected by computing root mean square value over a rolling window and comparing the computed value with a known threshold. Harmonic frequencies and symmetrical components are quantified by a known algorithm and compared with a known threshold. Incoming waveforms are stored to memory. All recorded and computed data is moved to non-volatile storage via direct memory access transfer in the event that a power quality event jeopardizes the operating power of the meter. Further, the meter provides a power supply utilizing high and low capacitive storage banks to supply sufficient energy to survive short duration power quality events which jeopardize the meter'"'"'s operating power.

Claims

1. A meter comprising first and second processors, first and second data busses, first and second memories, at least one bus arbiter responsive to said first and second processors and coupled with said first and second data busses and at least one transfer controller responsive to said first and second processors and coupled with said at least one bus arbiter, wherein each of said processors are coupled with a respective each said data busses and each of said data busses are coupled with a respective each of said memories, a method of transferring data between said first and second memories comprising:

requesting, from said first processor, at least one data transfer between said first memory and said second memory;

releasing control of said first data bus by said first processor;

signaling by said first processor to said at least one bus arbiter to couple said first data bus to said second data bus;

coupling said first data bus to said second data bus;

transferring data between said first memory and said second memory under control of said at least one transfer controller;

isolating said first data bus from said second data bus upon completion of said data transfer;

signaling from said at least one bus arbiter that said data transfer is complete; and

acquiring control of said first data bus by said first processor.

2. The method of claim 1 further comprising signaling by said at least-one bus arbiter to said at least one transfer controller that said first and second data busses are coupled and said first processor is ready for said data transfer.

3. The method of claim 1 further comprising signaling said first processor by said at least one transfer controller to initiate said data transfer.

4. The method of claim 1 further comprising signaling said second processor by said at least one transfer controller that said data transfer is complete.

5. The method of claim 1, wherein said meter includes a sensor configured to sense a power parameter in an energy circuit.

6. The method of claim 1, further comprising communicating said data from said second memory to a remote location.

7. A meter comprising first and second processors, first and second data busses, first and second memories, at least one bus arbiter responsive to said first and second processors and coupled with said first and second data busses, wherein each of said processors are coupled with a respective each said data busses and each of said data busses are coupled with a respective each of said memories, a method of transferring data between said first and second memories comprising:

requesting, from said first processor at least one data transfer between said first memory and said second memory;

releasing control of said first data bus by said first processor;

signaling by said first processor to said bus arbiter to couple said first data bus to said second data bus;

coupling said first data bus to said second data bus;

controlling of said first data bus by said second processor;

transferring data between said first memory and said second memory;

isolating said first data bus from said second data bus upon completion of said data transfer; and

acquiring control of said first data bus by said first processor.

8. The method of claim 7, wherein said meter includes a sensor configured to sense a power parameter in an energy circuit.

9. The method of claim 8 further comprising measuring the delivery of electrical energy through an electronic circuit by said meter.

10. The method of claim 7, wherein the transferring data between said first memory and said second memory comprises transferring a user programmable subset of said data from said first memory to said second memory.

11. The method of claim 7, wherein said first and second memories have a user programmable capacity.

12. The method of claim 7, further comprising communicating said data from said second memory to a remote location.

13. The method of claim 7, wherein said first and second memory store at least one cycle of digital samples.

14. The method of claim 7, further comprising signaling from said second processor that said data transfer is complete and said first and second data busses are isolated.

15. An electronic meter comprising:

a first memory;

a first processor coupled with the first memory by a first data bus;

a second memory;

a second processor coupled with the second memory by a second data bus; and

a transfer controller coupled with at least one of the first processor or the second processor, the transfer controller configured to facilitate a data transfer between the first memory to the second memory after the first processor requests the data transfer and the first data bus is coupled with the second data bus, wherein the first data bus and the second data bus are isolated after the data transfer.

16. The device of claim 15, wherein the electronic device is an energy meter for measuring the delivery of electrical energy through an electric circuit.

17. The device of claim 16 further comprising:

a sensor coupled with the electric circuit and operative to sense a power parameter in the electric circuit and generate an analog signal indicative of the power parameter; and

an analog to digital converter coupled with the sensor and operative to convert said analog signal to one or more digital samples.

18. The device of claim 15, wherein the first processor is configured to release control of the first data bus for the data transfer.

19. The device of claim 15, wherein the second processor is configured to control the first data bus for the data transfer.

20. An energy meter for measuring the delivery of electrical energy through an electric circuit, said meter comprising:

a sensor coupled with said electric circuit and operative to sense a power parameter in said electric circuit and generate an analog signal indicative of said power parameter;

an analog to digital converter coupled with said sensor and operative to convert said analog signal to one or more digital samples;

a first memory coupled with said analog to digital converter and operative to receive and store said one or more digital samples;

a first processor coupled with said first memory by a first data bus;

a second memory;

a second processor coupled with said second memory by a second data bus; and

a bus arbiter coupled with said first and second data busses and configured to couple said first data bus with said second data bus for a data transfer between said first memory and said second memory, further wherein said second processor uses said bus arbiter to access said first data bus for said data transfer.

21. The device of claim 20, wherein the bus arbiter is configured to isolate said first data bus from said second data bus.