Memory device with pre-fetch circuit and pre-fetch method
First Claim
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1. A memory device comprising:
- a first memory block and a second memory block having memory cells arranged in rows and columns;
a first selector coupled to the first memory block to select a row of the memory cells;
a group of amplifiers coupled to the first memory block to at least one of read data from and write data to the selected row;
a buffer, coupled to the group of amplifiers, comprising a plurality of latches having sufficient capacity to hold data corresponding to the selected row of memory cells, wherein a portion of the latches are shared between the first memory block and the second memory block; and
a second selector for selectively activating one of a first bank of switches and a second bank of switches to associate the portion of the latches with one of the first memory block and the second memory block, respectively.
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Abstract
A memory device includes plural memory blocks, each memory block having memory cells arranged in wordlines and bitlines and a selector to select a wordline of memory cells. A group of first sense amplifiers are coupled to each memory block to at least one of read data from and write data to the selected wordline. A buffer of latches are coupled to the group of first sense amplifiers and have sufficient capacity to hold data corresponding to the selected wordline of memory cells.
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Citations
20 Claims
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1. A memory device comprising:
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a first memory block and a second memory block having memory cells arranged in rows and columns; a first selector coupled to the first memory block to select a row of the memory cells; a group of amplifiers coupled to the first memory block to at least one of read data from and write data to the selected row; a buffer, coupled to the group of amplifiers, comprising a plurality of latches having sufficient capacity to hold data corresponding to the selected row of memory cells, wherein a portion of the latches are shared between the first memory block and the second memory block; and a second selector for selectively activating one of a first bank of switches and a second bank of switches to associate the portion of the latches with one of the first memory block and the second memory block, respectively. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A memory device comprising:
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a first memory block and a second memory block having memory cells arranged in rows and columns; a first set of amplifiers coupled to the rows of memory cells in the first memory block to at least one of read data from and write data to the rows of memory cells; a buffer, coupled to the first set of amplifiers, comprising a plurality of latches to hold data corresponding to one of the rows of memory cells, wherein a portion of the latches are shared between the first memory block and the second memory block; a second set of amplifiers coupled to the buffer to at least one of read data from and write data to the buffer; and a selector for selectively activating one of a first bank of switches and a second bank of switches to associate the portion of the latches with one of the first memory block and the second memory block, respectively. - View Dependent Claims (8, 9)
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10. A method of reading data from a first memory block and a second memory block having rows of memory cells for storing data and an output line, the method comprising:
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selecting a first one of the rows of memory cells; selectively activating one of a first bank of switches and a second bank of switches to associate a portion of a group of latches with one of the first memory block and the second memory block, respectively; transferring, in a single operation, the data stored in the selected first row of memory cells through a group of amplifiers to the group of latches; and holding the transferred data in the group of latches. - View Dependent Claims (11, 12, 13, 14)
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15. A method of writing data to a first memory block and a second memory block having rows of memory cells for storing data and an input line, the method comprising:
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selecting a first one of the rows of memory cells to receive data; selectively activating one of a first bank of switches and a second bank of switches to associate a portion of a group of latches with one of the first memory block and the second memory block, respectively; reading currently held data from the memory cells of the selected first row to the group of latches; transferring data from the input line to at least one latch of the group of latches; and writing, in a single operation, the data held in the group of latches through a group of amplifiers to the selected first row of memory cells. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification