Dual source real time clock synchronization system and method

• US 7,343,255 B2
• Filed: 07/07/2005
• Issued: 03/11/2008
• Est. Priority Date: 07/07/2004
• Status: Expired due to Fees

• Current Assignee: Itron, Inc.
• Original Assignee: Itron, Inc.
• Inventors: Nagy, Christopher J., Osterloh, Christopher L.
• Primary Examiner(s): WACHSMAN, HAL D
• Application Number:
  US11/176,937
• Publication Number:
  US 20060009927A1
• Time in Patent Office: 978 Days
• Field of Search: 702 60- 62, 702/57, 702/64, 702/65, 702/79, 702/106, 702/107, 702/125, 702/122, 702/187, 702/176, 702/178, 702/189
• US Class Current: 702/62
• CPC Class Codes: G08C 17/02 using a radio link
• CPC Class Codes: G08C 2201/51 Remote controlling of devices based on replies, status thereof

Abstract

A dual source real time clock (RTC) synchronization system and method for implementation within automatic meter reading (AMR) systems that provide system-wide device time synchronization. In one embodiment, a microcontroller-implemented RTC counts elapsed seconds from a pre-determined system timestamp using a low-speed, low-accuracy crystal. A second source is used to compensate for the low-speed, low-accuracy crystal. This second source comprises a high speed clock in one embodiment. This dual source RTC system can synchronize the endpoint device.

Claims

1. A method of synchronizing an endpoint device adapted for radio frequency (RF) communications in an automatic meter reading (AMR) system, the method comprising the steps of:

counting elapsed time from a system timestamp by a first clock through a plurality of count cycles having a fixed count value;

counting elapsed time by a second clock through a subsequent count cycle having a fixed count value, wherein an accuracy of the second clock is higher than an accuracy of the first clock;

determining an overflow count and an offset count based on a maximum count value of the second clock, wherein the maximum count value resets when reached and the overflow count equals the number of times the maximum count value of the second clock has been reached and the offset count equals number of counts reached after the last maximum count value;

calculating a calculated count value of a final count cycle from the offset count;

compensating for a synchronization error of the first clock by adjusting the final count cycle from a nominal default count value to the calculated count value; and

using the first clock as compensated for the synchronization error as a source of clocking signals for the endpoint device in the AMR system.

2. The method of claim 1, wherein the calculated count value of the final count cycle is calculated using an estimated piecewise linearization method.

3. The method of claim 1, wherein the step of counting elapsed time from a system time stamp by a first clock further comprises counting through three count cycles having a first fixed count value.

4. The method of claim 3, wherein the step of counting elapsed time by a second clock further comprises counting though a fourth count cycle having a second fixed count value, and wherein the nominal default count value is the second fixed count value.

5. The method of claim 4, wherein the three count cycles each comprise about one second and the fourth and final count cycles each comprise about one-half second.

6. The method of claim 5, wherein the first fixed count value is 32,767 and the second fixed count value and the nominal default count value are each 16,384.

7. The method of claim 1, wherein the steps are performed during a periodic read of the endpoint device as part of the AMR system.

8. A utility meter endpoint device adapted for a radio frequency (RF) communication automatic meter reading (AMR) system, the utility meter endpoint device comprising:

a communications unit operatively coupled to a utility meter and comprising communications circuitry adapted for periodic RF communications with a reader; and

a microcontroller comprising a real time clock (RTC) and a counter and electrically coupled to a power source and the communications circuitry, the RTC comprising a first oscillator and the counter comprising a second oscillator, the second oscillator having a higher accuracy than the first oscillator,

wherein the microcontroller is operable to calculate an adjustable final count cycle based on the counter and the second oscillator after a plurality of fixed count cycles during a periodic RF communication and use the calculated adjustable final count cycle to compensate the RTC to maintain synchronization at an accuracy better than an accuracy of the first oscillator.

9. The device of claim 8, wherein the power source is common to the utility meter and electrically coupled to the communications unit.

10. The device of claim 8, wherein the reader is selected from the set consisting of a fixed network reader, a mobile reader, and a handheld reader.

11. The device of claim 8, wherein the plurality of fixed count cycles comprise first, second, third, and fourth count cycles, the first, second, and third count cycles having a first fixed count value and the fourth count cycle having a second fixed count value.

12. The device of claim 11, wherein the adjustable final count cycle has a nominal count value equal to the second fixed count value.

13. The device of claim 11, wherein the counter has a maximum count value and is operable to count during the fourth count cycle to determine an offset value used by the microcontroller to calculate the adjustable final count cycle, wherein an offset value is a counter value at the end of the fourth count cycle.

14. The device of claim 8, wherein the adjustable final count cycle is calculated by the microcontroller using an estimated piecewise linearization method.

15. The device of claim 8, wherein the second oscillator is used by the communications circuitry and is wirelessly synchronized to an external reference time signal.

16. A synchronization system for an endpoint device adapted for radio frequency (RF) communications in an automatic meter reading (AMR) system, the synchronization system comprising:

a microcontroller;

a first oscillator in operable communication with the microcontroller; and

a second oscillator in operable communication with the microcontroller, the second oscillator wirelessly synchronizable with an external reference time signal and having a higher speed and a higher accuracy than the first oscillator,

wherein the microcontroller operably determines an offset count value of the second oscillator during a fixed count cycle and synchronizes the first oscillator to the second oscillator during an RF communication by calculating an adjustable final count cycle from the offset count value.

17. The system of claim 16, wherein the AMR system is a mobile system.

18. The system of claim 17, wherein the synchronization system provides less than about two minutes error per month.

19. The system of claim 18, wherein the mobile system is a handheld system.

20. The system of claim 16, wherein the AMR system is a fixed network system.

21. The system of claim 20, wherein the synchronization system provides less than about ten milliseconds of drift in a period of five minutes.