Scalable distributed memory and I/O multiprocessor systems and associated methods
First Claim
1. A multiprocessor system comprising:
- at least one processing module;
at least one input/output module; and
an interconnect network to communicatively couple the at least one processing module with the at least one input/output module, the interconnect network includingat least two bridges to send and receive transactions from the at least one input/output module and the at least one processing module; and
at least two crossbar switches to route the transactions over a bus between the at least two bridges.
0 Assignments
0 Petitions
Accused Products
Abstract
A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
-
Citations
20 Claims
-
1. A multiprocessor system comprising:
-
at least one processing module; at least one input/output module; and an interconnect network to communicatively couple the at least one processing module with the at least one input/output module, the interconnect network including at least two bridges to send and receive transactions from the at least one input/output module and the at least one processing module; and at least two crossbar switches to route the transactions over a bus between the at least two bridges. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A multiprocessor system, comprising:
-
at least one processing module; at least one input/output module; one or more buses to communicatively couple the at least one processing module and the at least one input/output module; at least one interconnect component coupled to the at least one processing module and the at least one input/output module, the interconnect component to support a protocol of the one or more buses between the at least one processing module and the at least one input/output module; wherein the at least one interconnect component may be separate from both the at least one processing module and the at least one input/output module. - View Dependent Claims (10, 11, 12, 13, 14)
-
-
15. A integrated circuit comprising:
-
at least one processing module; at least one input/output module; a crossbar router; and a bridge communicatively coupled to the crossbar router, the bridge to packetize transactions between the at least one processing module and the at least one input/output module in a format that is compatible with the crossbar router. - View Dependent Claims (16, 17)
-
-
18. A method of operating a multiprocessor system including at least one processing module, at least one input/output module, and at least one interconnect network communicatively coupling the at least one processing module and the at least one input/output module, the method comprising:
-
the at least one interconnect network utilizing at least two bridges to send and receive transactions between the at least one processing module and the at least one input/output module; and the at least one interconnect network utilizing at least two crossbar switches to route the transactions over a bus between the at least two bridges. - View Dependent Claims (19, 20)
-
Specification