Method for patterning electrically conducting poly(phenyl acetylene) and poly(diphenyl acetylene)

• US 7,344,912 B1
• Filed: 03/01/2005
• Issued: 03/18/2008
• Est. Priority Date: 03/01/2005
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Okoronyanwu, Uzodinma
• Primary Examiner(s): Geyer, Scott B.
• Assistant Examiner(s): NIKMANESH, SEAHVOSH J
• Application Number:
  US11/069,181
• Time in Patent Office: 1,113 Days
• Field of Search: 438/706, 438/597, 438/623, 438/637, 438/652, 438/653, 438/99, 438/72, 438/800
• US Class Current: 438/85
• CPC Class Codes: H10K 71/60 Forming conductive regions or layers, e.g. electrodes

Abstract

Disclosed are methods of fabricating a memory cell structure. More specifically, a copper substrate, including but not limited to copper contacts and/or bit lines, can be formed within a metal-containing layer, for example. Optionally, one or more via openings can then be formed in an overlying dielectric layer to expose one or more of the copper contacts and/or bit lines. Copper sulfide material can be formed thereon. Alternatively, a portion of the exposed copper can be converted to copper sulfide (e.g., Cu₂S₂ or Cu₂S). The copper sulfide material can then be exposed to a vapor phase monomer to facilitate selective growth of a conducting polymer.

Claims

1. A method of fabricating a memory cell structure comprising:

providing a copper substrate;

forming one or more copper sulfide regions on the copper substrate;

exposing the one or more copper sulfide regions by way of a vapor phase monomer to facilitate growing a conducting polymer material on surfaces of the copper sulfide regions; and

forming at least one of plugs, shallow trench isolation regions, and channel stop regions below the conducting polymer material.

2. The method of claim 1, further comprising:

forming an amorphous carbon layer over the copper substrate before forming the one or more copper sulfide regions;

forming an antireflective layer over the amorphous carbon layer;

forming one or more photoresist structures on the antireflective layer;

selectively etching the antireflective layer using the one or more photoresist structures; and

selectively etching the amorphous carbon layer using the patterned antireflective layer as a hardmask.

3. The method of claim 2, further comprising:

depositing a dielectric material to facilitate planarizing underlying structures;

removing the antireflective layer; and

exposing one or more surfaces of the copper substrate by removing amorphous carbon in O₂ plasma ash to facilitate subsequent formation of copper sulfide regions.

4. The method of claim 3, wherein the underlying structures comprises a hardmask region overlying an amorphous carbon region.

5. The method of claim 3, wherein the dielectric material comprises at least one of a low temperature dielectric or an organic low-k dielectric.

6. The method of claim 1, further comprising forming one or more layers overlying the copper sulfide or conducting polymer material.

7. The method of claim 6, wherein the one or more layers comprises a dielectric layer that includes at least one of oxide, nitride, TEOS, FTEOS, and organic materials.

8. The method of claim 6, wherein the one or more layers comprises tungsten, titanium, tantalum, titanium nitride, amorphous carbon, aluminum, indium-tin oxide, platinum, zinc, nickel, iron, manganese, magnesium, gold, chromium, metal silicides, alloys thereof, and/or any combination thereof.

9. The method of claim 8, wherein alloys comprise nickel-containing alloys, brass, stainless steel, magnesium-silver alloy, and/or combinations thereof.

10. The method of claim 8, wherein the one or more layers comprise a word line, a barrier layer, a metal-containing layer, and an insulating layer.

11. The method of claim 1, wherein the conducting polymer material comprises any one of polyphenol acetylene, poly-acetylene, poly-diphenyl acetylene, polyaniline, polythiophene, polyporphyrins, porphyrinic macrocycles, thiol derivatized polyporphyrins, polymetallocenes, polyferrocenes, polyphthalocyanines, polyvinylenes, polypyrroles, and poly-(p-phenylene vinylene, and/or combinations thereof, and/or monomers thereof.

12. The method of claim 1, further comprising forming channel stop regions below the conducting polymer material.

13. The method of claim 1, wherein exposing the one or more copper sulfide regions by way of a vapor phase monomer comprises reacting H₂S with an exposed surface of the copper substrate.

14. A method of fabricating a memory cell structure comprising:

providing a semiconductor substrate;

forming a copper layer overlying the semiconductor substrate;

forming one or more vias in the copper layer;

forming copper sulfide material in a bottom portion of the one or more vias in the copper layer, whereby the copper sulfide contacts a surface of the copper layer and reacts with H₂S; and

growing a conducting polymer material on exposed copper sulfide surface from a vapor phase monomer.

15. The method of claim 14, further comprising forming one or more layers overlying the copper sulfide or conducting polymer material.

16. The method of claim 15, wherein the one or more layers comprises a dielectric layer that includes at least one of oxide, nitride, TEOS, FTEOS, and organic materials.

17. The method of claim 14, wherein the conducting polymer material comprises any one of polyphenol acetylene, poly-acetylene, poly-diphenyl acetylene, polyaniline, polythiophene, polyporphyrins, porphyrinic macrocycles, thiol derivatized polyporphyrins, poly-metallocenes, polyferrocenes, polyphthalocyanines, polyvinylenes, polypyrroles, and poly-(p-phenylene vinylene, and/or combinations thereof, and/or monomers thereof.

18. The method of claim 14, wherein the one or more layers comprises tungsten, titanium, tantalum, titanium nitride, amorphous carbon, aluminum, indium-tin oxide, platinum, zinc, nickel, iron, manganese, magnesium, gold, chromium, metal silicides, alloys thereof, and/or any combination thereof.

19. The method of claim 18, wherein alloys comprise nickel-containing alloys, brass, stainless steel, magnesium-silver alloy, and/or combinations thereof.

20. A system for fabricating a memory cell structure comprising:

means for providing a copper substrate;

means for forming one or more copper sulfide regions on the copper substrate; and

means for exposing the one or more copper sulfide regions with a vapor phase monomer to facilitate growing a conducting polymer material on surfaces of the copper sulfide regions;

means for forming an amorphous carbon layer over the copper substrate before

means for forming the one or more copper sulfide regions;

means for forming an antireflective layer over the amorphous carbon layer;

forming one or more photoresist structures on the antireflective layer;

means for selectively etching the antireflective layer using the one or more photoresist structures; and

means for selectively etching the amorphous carbon layer using the patterned antireflective layer as a hardmask.