CMOS transistor and method of manufacture thereof

• US 7,344,934 B2
• Filed: 12/06/2004
• Issued: 03/18/2008
• Est. Priority Date: 12/06/2004
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Li, Hong-Jyh
• Primary Examiner(s): Lebentritt; Michael
• Assistant Examiner(s): Lee; Kyoung
• Application Number:
  US11/005,292
• Publication Number:
  US 20060118879A1
• Time in Patent Office: 1,198 Days
• Field of Search: None
• US Class Current: 438/199
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. An aluminum-based material is used as a gate dielectric material of a PMOS device, and a hafnium-based material is used as a gate dielectric material of an NMOS device. A thin layer of silicon a few monolayers or a sub-monolayer thick is formed over the gate dielectric materials, before forming the gates. The thin layer of silicon bonds with the gate dielectric material and pins the work function of the transistors. A gate material that may comprise a metal in one embodiment is deposited over the thin layer of silicon. A CMOS device having a symmetric V_t for the PMOS and NMOS FETs is formed.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

providing a workpiece, the workpiece comprising a first region and a second region;

forming a first transistor in the first region of the workpiece, the first transistor including a first gate dielectric material;

forming a second transistor in the second region of the workpiece, the second transistor including a second gate dielectric material; and

exposing the first gate dielectric material and the second gate dielectric material to a silicon-containing substance to form a first silicon layer over the first gate dielectric material and a second silicon layer over the second gate dielectric material, wherein the first silicon layer and the second silicon layer pin the work function of the first transistor and the second transistor, respectively.

2. The method according to claim 1, wherein forming the second transistor comprises forming a hard mask over the first region of the workpiece, depositing the second gate dielectric material over the hard mask and the second region of the workpiece, depositing a second gate material over the second gate dielectric material, removing the second gate material, second gate dielectric material, and the hard mask from over the first region of the workpiece, leaving the second gate material and the second gate dielectric material residing over the second region of the workpiece, wherein exposing the second gate dielectric material to the silicon-containing substance is after depositing the second gate dielectric material;

and wherein forming the first transistor comprises depositing the first gate dielectric material over the first region of the workpiece and over the second gate material over the second region of the workpiece, depositing the first gate material over the first gate dielectric material, and removing the first gate material and the first gate dielectric material from over the second region of the workpiece, leaving the first gate material and the first gate dielectric material over the first region of the workpiece, wherein exposing the first gate dielectric to the silicon-containing substance is after depositing the first gate dielectric material.

3. The method according to claim 2, wherein removing the second gate material, second gate dielectric material, and the hard mask from over the first region of the workpiece comprises depositing a first photoresist over the second gate material, removing the first photoresist from over the first region of the workpiece, removing the second gate material, second gate dielectric material, and the hard mask from the first region using the first photoresist as a mask, and removing the first photoresist;

and wherein removing the first gate material and the first gate dielectric material from over the second region of the workpiece comprises depositing a second photoresist over the first gate material, removing the second photoresist from over the second region of the workpiece, removing the first gate material and the first gate dielectric material from the second region using the second photoresist as a mask, and removing the second photoresist.

4. The method according to claim 1, wherein the workpiece has a top surface, wherein forming the first gate dielectric material comprises forming the first gate dielectric material over the entire top surface of the workpiece, further comprising forming a first gate material over the first gate dielectric material, depositing a hard mask over the first gate material, and using the hard mask as a mask while removing the first gate material and the first gate dielectric material from over the second region of the workpiece, further comprising forming the second gate dielectric material over the first gate material in the first region and over the workpiece in the second region, and forming a second gate material over the second gate dielectric material, and removing the second gate material and the second gate dielectric material from over the first gate material.

5. The method according to claim 1, wherein forming the first transistor comprises forming a first transistor having a first gate dielectric material comprising aluminum, wherein forming the first transistor comprises forming a p channel metal oxide semiconductor (PMOS) transistor, and wherein forming the second transistor comprises forming a second transistor having a second gate dielectric material comprising hafnium, wherein forming the second transistor comprises forming an n channel metal oxide semiconductor (NMOS).

6. The method according to claim 1, wherein exposing the first gate dielectric material and the second gate dielectric material to a silicon-containing substance comprises exposing the first gate dielectric material and the second gate dielectric material to SiH₄, SiCl₄ or Si[N(CH₃)C₂H₅]₄.

7. The method according to claim 1, wherein exposing the first gate dielectric material and the second gate dielectric material to a silicon-containing substance comprises forming a first silicon layer over the first gate dielectric material and forming a second silicon layer over the second gate dielectric material.

8. The method according to claim 7, wherein forming the first silicon layer and forming the second silicon layer comprise forming about 1 to 10 monolayers or a sub-monolayer of silicon.

9. The method according to claim 7, wherein forming the first silicon layer and forming the second silicon layer comprise forming a layer having a thickness of about 30 Å

or less.

10. The method according to claim 1, further comprising forming a first gate over the first gate dielectric material, and forming a second gate over the second gate dielectric material, wherein the first gate and the second gate comprise a semiconductor material or a metal.

11. The method according to claim 10, wherein forming the first gate and forming the second gate comprise forming TiN, HfN, TaN, ZrN, LaN, TiN, HfN, TaN, RuN, WN, W, TiSiN, HfSiN, TaSiN, ZrSiN, LaSiN, TiSiN, HfSiN, TaSiN, RuSiN, WSiN, WSi, a semiconductive material, or combinations thereof.

12. The method according to claim 10, wherein forming the first gate and forming the second gate comprise forming a gate having a thickness of about 10 Å

to about 1000 Å

.

13. The method according to claim 10, wherein forming the first gate and the second gate comprise forming a first gate and a second gate comprising the same material, or forming a first gate and a second gate from the same material layer.

14. The method according to claim 1, wherein the first region of the workpiece is proximate the second region of the workpiece, wherein the semiconductor device comprises a complimentary metal oxide semiconductor (CMOS) device, wherein forming the first transistor comprises forming a p channel metal oxide semiconductor transistor (PMOS) device, and wherein forming the second transistor comprises forming an n channel metal oxide semiconductor transistor (NMOS) device, wherein the first transistor and the second transistor comprise substantially symmetric threshold voltages V_t.

15. The method according to claim 14, further comprising lightly doping the first region with an N dopant and lightly doping the second region with a P dopant, further comprising forming a first source and a first drain of the first transistor by implanting a P dopant into the first region of the workpiece, and further comprising forming a second source and a second drain of the second transistor by implanting N dopants into the second region of the workpiece.

16. The method according to claim 1, wherein forming the first gate dielectric material comprises forming a first insulating layer over the first region and the second region of the workpiece, and forming a second insulating layer over the first insulating layer over the first region, but not the second region of the workpiece.

17. The method according to claim 16, wherein the first transistor comprises a PMOS transistor and the second transistor comprises an NMOS transistor, wherein forming the first insulating layer comprises depositing a high-k dielectric material, wherein forming the second insulating layer comprises forming an aluminum-containing material, and wherein forming the first gate material comprises depositing the first gate material over and abutting the second insulating layer.

18. The method according to claim 17, wherein forming the first insulating layer comprises forming a hafnium-based layer.

19. The method according to claim 16, further comprising depositing a third insulating layer over the first insulating layer, after forming the second insulating layer.

20. The method according to claim 1, wherein forming the first transistor comprises forming a transistor having a first gate dielectric comprising Si₃N₄, Al₂O₃, Ta₂O₅, HfO₂, TiO₂, HfSiO_x, ZrO₂, ZrSiO_x, La₂O₃, CeO₂, Bi₄Si₂O₁₂, WO₃, Y₂O₃, LaAlO₃, BST (Ba_(a-x)Sr_xTiO₃), PST (PbSc_xTa_(1-a)O₃), PZN (PbZn_xNb_(1-x)O₃), PZT (PbZr_xTi_(1-x)O₃), PMN (PbMg_xNb_(1-x)O₃), or combinations thereof, and wherein forming the second transistor comprises forming a transistor having a second gate dielectric comprising Si₃N₄, Al₂O₃, Ta₂O₅, HfO₂, TiO₂, HfSiO_x, ZrO₂, ZrSiO_x, La₂O₃, CeO₂, Bi₄Si₂O₁₂, WO₃, Y₂O₃, LaAlO₃, BST (Ba_(a-x)Sr_xTiO₃), PST (PbSc_xTa_(1-a)O₃), PZN (PbZn_xNb_(1-x)O₃), PZT (PbZr_xTi_(1-x)O₃), PMN (PbMg_xNb_(1-x)O₃), or combinations thereof.

33. The method of claim 19, wherein the first insulating layer and the third insulating layer comprise the same material.

21. A method of making a semiconductor device, the method comprising:

forming a first transistor in a first region of a workpiece, the first transistor including a first source and a first drain disposed in the workpiece, a first channel region disposed between the first source and the first drain, a first gate dielectric disposed over the first channel region, the first gate dielectric comprising a first material, a first silicon layer disposed over the first gate dielectric, and a first gate disposed over the first silicon layer; and

forming a second transistor in a second region of the workpiece, the second transistor including a second source and a second drain disposed in the workpiece, a second channel region disposed between the second source and the second drain, a second gate dielectric disposed over the second channel region, the second gate dielectric comprising a second material, a second silicon layer disposed over the second gate dielectric, and a second gate disposed over the second silicon layer, wherein the first transistor comprises a work function that is pinned by the first silicon layer, and wherein the second transistor comprises a work function that is pinned by the second silicon layer.

22. The method according to claim 21, wherein the first silicon layer and the second silicon layer comprise about 1 to 10 monolayers or a sub-monolayer of silicon.

23. The method according to claim 21, wherein the first silicon layer and the second silicon layer comprise a thickness of about 30 Å

or less.

24. The method according to claim 21, wherein the first transistor comprises a p channel metal oxide semiconductor (PMOS) transistor and the second transistor comprises an n channel metal oxide semiconductor (NMOS) transistor, wherein the first transistor and the second transistor comprise substantially symmetric threshold voltages V_t.

25. The method according to claim 24, wherein the first gate dielectric comprises an aluminum-based material, and wherein the second gate dielectric comprises a hafnium-based material.

26. The method according to claim 21, wherein the first gate dielectric comprises a first insulating layer disposed over the first channel, and a second insulating layer disposed over the first insulating layer, and wherein the second gate dielectric comprises the first insulating layer.

27. The method according to claim 26, wherein the first insulating layer comprises a high-k dielectric material, and wherein the second insulating layer comprises an aluminum-based material, wherein the second insulating layer is disposed beneath and abuts the first gate.

28. The method according to claim 21, wherein the first gate dielectric and the second gate dielectric each have a thickness of about 5 to 60 Angstroms.

29. The method according to claim 21, wherein the first gate dielectric and the second gate dielectric comprise Si₃N₄, Al₂O₃, Ta₂O₅, HfO₂, TiO₂, HfSiO_x, ZrO₂, ZrSiO_x, La₂O₃, CeO₂, Bi₄Si₂O₁₂, WO₃, Y₂O₃, LaAlO₃, BST (Ba_(a-x)Sr_xTiO₃), PST (PbSc_xTa_(1-a)O₃), PZN (PbZn_xNb_(1-x)O₃), PZT (PbZr_xTi_(1-x)O₃), PMN (PbMg_xNb_(1-x)O₃), or combinations thereof.

30. The method according to claim 21, wherein the first gate and the second gate comprise TiN, HfN, TaN, ZrN, LaN, TiN, HfN, TaN, RuN, WN, W, TiSiN, HfSiN, TaSiN, ZrSiN, LaSiN, TiSiN, HfSiN, TaSiN, RuSiN, WSiN, WSi, a semiconductive material, or combinations thereof.

31. The method according to claim 21, wherein the first gate and the second gate each have a thickness of about 10 Å

to about 1000 Å

.

32. The method according to claim 21, wherein the first gate and the second gate comprise the same material.