Method for forming a trench MOSFET having self-aligned features

• US 7,344,943 B2
• Filed: 04/20/2005
• Issued: 03/18/2008
• Est. Priority Date: 05/20/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Herrick, Robert, Losee, Becky, Probst, Dean
• Primary Examiner(s): Tran, Long K.
• Application Number:
  US11/111,305
• Publication Number:
  US 20050191794A1
• Time in Patent Office: 1,063 Days
• Field of Search: 438/637, 438/700, 438/259, 438/270, 438/274, 438/672, 257/330
• US Class Current: 438/259
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 257/905 Plural dram cells share common contact or common trench

Abstract

A semiconductor device is formed as follows. A plurality of trenches is formed in a silicon layer. An insulating layer filling an upper portion of each trench is formed. Exposed silicon is removed from adjacent the trenches to expose an edge of the insulating layer in each trench, such that the exposed edge of the insulating layer in each trench defines a portion of each contact opening formed between every two adjacent trenches.

Claims

1. A method of forming a semiconductor device, comprising:

forming a plurality of trenches in a silicon layer;

forming a first doped region of a first conductivity type in an upper portion of the silicon layer;

forming an insulating layer within each trench such that a top surface of the insulating layer is substantially coplanar with a top surface of the first doped region, the insulating layer in each trench extending directly over a portion of the first doped region adjacent each trench sidewall; and

removing exposed silicon from adjacent each trench until, of the first doped region, only the portions adjacent the trench sidewalls remain, the remaining portions of the first doped region adjacent the trench sidewalls forming source regions which are self-aligned to the trenches.

2. The method of claim 1 wherein the step of removing exposed silicon forms a contact opening between every two adjacent trenches.

3. The method of claim 2 further comprising:

prior to forming the first doped region, forming a second doped region of a second conductivity type in the upper portion of the silicon layer.

4. The method of claim 3 further comprising:

implanting dopants through the contact openings to form a heavy body region of a second conductivity type in the second doped region.

5. The method of claim 4 further comprising:

forming a metal layer to electrically contact the source regions and the heavy body region through the contact opening.

6. The method of claim 1 further comprising:

prior to forming the insulating layer, forming a gate electrode partially filling each trench.

7. A method of fabricating a semiconductor device, comprising:

forming a plurality of trenches in a silicon layer;

forming a gate electrode partially filling each trench;

forming a first doped region of a first conductivity type in an upper portion of the silicon layer;

forming an insulating layer within each trench such that a top surface of the insulating layer is substantially coplanar with a top surface of the first doped region, each trench having a contour such that the insulating layer in each trench extends directly over a portion of the first doped region adjacent each trench sidewall; and

removing exposed silicon from between adjacent trenches such that;

     1) a contact opening is formed between every two adjacent trenches, and

     2) of the first doped region, only the portion adjacent each trench sidewall remains, the portion of the first doped region remaining adjacent each trench sidewall forming a source region.

8. The method of claim 7 wherein the step of removing exposed silicon is carried out without using a mask so that the contact opening between every two adjacent trenches and the portion of the first doped region remaining adjacent each trench sidewall are self-aligned.

9. The method of claim 7 further comprising:

prior to forming the first doped region, forming a second doped region of a second conductivity type in the upper portion of the silicon layer.

10. The method of claim 9 further comprising:

implanting dopants through the contact openings to form a heavy body region of a second conductivity type in the second doped region between adjacent trenches.

11. The method of claim 10 further comprising:

forming a metal layer to electrically contact the source regions and the heavy body region through the contact opening.