Method of manufacturing a drain side gate trench metal-oxide-semiconductor field effect transistor

• US 7,344,945 B1
• Filed: 12/22/2004
• Issued: 03/18/2008
• Est. Priority Date: 05/13/2004
• Status: Expired due to Fees

• Current Assignee: Vishay-Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Pattanayak, Deva, Wong, Ronald, Bai, Yuming, Lui, Kam-Hong, Qi, Jason (Jianhai)
• Primary Examiner(s): Smith; Zandra V.
• Assistant Examiner(s): Duong; Khanh
• Application Number:
  US11/023,327
• Time in Patent Office: 1,182 Days
• Field of Search: None
• US Class Current: 438/270
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/781 Inverted VDMOS transistors, i.e. Source-Down VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Embodiments of the present invention provide a striped or closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET). The striped or closed cell TMOSFET comprises a source region, a body region disposed above the source region, a drift region disposed above the body region, a drain region disposed above the drift region. A gate region is disposed above the source region and adjacent the body region. A gate insulator region electrically isolates the gate region from the source region, body region, drift region and drain region. The body region is electrically coupled to the source region.

Claims

1. A method of fabrication a striped cell trench metal-oxide-semiconductor field effect transistor (TMOSFET) comprising:

depositing a first semiconductor layer upon a semiconductor substrate, wherein said first semiconductor layer is doped with a first type of impurity and said semiconductor substrate is doped with a second type of impurity;

depositing a second semiconductor layer upon said first semiconductor layer;

etching a first plurality of trenches in said first semiconductor layer, said second semiconductor layer and a portion of said semiconductor substrate, wherein said first plurality of trenches are substantially parallel with respect to each other;

forming a first dielectric layer in said first plurality of trenches;

depositing a first polysilicon layer in said first plurality of trenches;

depositing a second dielectric layer in said first plurality of trenches upon said first polysilicon layer;

doping said first semiconductor layer with said first type of impurity;

doping a portion of said second semiconductor layer, opposite said first semiconductor layer, with said second type of impurity at a first concentration; and

etching a second plurality of trenches in said first semiconductor layer said second semiconductor layer and a portion of said semiconductor substrate, wherein said second plurality of trenches are substantially parallel with respect to each other and disposed between said first plurality of trenches;

doping a portion of said first semiconductor layer proximate said second plurality of trenches;

forming a silicide along said semiconductor substrate and said first semiconductor layer in said second plurality of trenches; and

depositing a third dielectric layer in said second plurality of trenches.

2. The method according to claim 1, wherein said depositing said first semiconductor layer comprises epitaxial depositing silicon doped with boron.

3. The method according to claim 1, wherein said depositing said second semiconductor layer comprises epitaxial depositing silicon doped with boron.

4. The method according to claim 3, wherein doping said first semiconductor layer with said first type of impurity comprises implanting boron.

5. The method according to claim 1, wherein said depositing said second semiconductor layer comprises epitaxial depositing silicon doped with phosphorous or arsenic.

6. The method according to claim 1, wherein doping a portion of said second semiconductor layer, opposite said first semiconductor layer, with said second type of impurity comprises implanting phosphorous or arsenic.

7. The method according to claim 1, further comprising doping said second semiconductor layer with said second type of impurity at a second concentration prior to said doping said portion of said second semiconductor layer, wherein said first concentration is greater than said second concentration.

8. The method according to claim 1, wherein forming said silicide comprises:

sputtering a metal film along said semiconductor substrate and said first semiconductor layer in said second plurality of trenches; and

thermal cycling said metal film, said semiconductor substrate and said first semiconductor layer.

9. The method according to claim 1, further comprising:

depositing a second polysilicon layer in said first plurality of trenches between said first polysilicon layer and said second dielectric layer; and

forming a fourth dielectric layer between said first polysilicon layer and second polysilicon layer.

10. A method of fabrication a closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET) comprising:

depositing a first semiconductor layer upon a semiconductor substrate, wherein said first semiconductor layer is doped with a first type of impurity and said semiconductor substrate is doped with a second type of impurity;

depositing a second semiconductor layer upon said first semiconductor layer;

etching a plurality of trenches in said first semiconductor layer, said second semiconductor layer and a portion of said semiconductor substrate, wherein a first set of said plurality of trenches are substantially parallel with respect to each other and a second set of said plurality of trenches are substantially normal-to-parallel with respect to the first set of said plurality of trenches;

forming a first dielectric layer in said first semiconductor layer, said second semiconductor layer and said substrate proximate said plurality of trenches proximate said plurality of trenches;

depositing a first polysilicon layer in said first plurality of trenches;

depositing a second dielectric layer in said first plurality of trenches upon said first polysilicon layer;

doping said first semiconductor layer with said first type of impurity;

doping said second semiconductor layer with said second type of impurity at a first concentration;

doping a portion of said second semiconductor layer, opposite said first semiconductor layer, with said second type of impurity at a second concentration;

etching a plurality of openings in said first semiconductor layer said second semiconductor layer and a portion of said semiconductor substrate, wherein said openings are disposed within each of a plurality of cells formed between said plurality of trenches;

doping a portion of said first semiconductor layer proximate said plurality of openings;

forming a silicide along said semiconductor substrate and said first semiconductor layer in said plurality of openings; and

depositing a third dielectric layer in said plurality of openings.

11. The method according to claim 10, wherein:

said depositing said first semiconductor layer comprises epitaxial depositing silicon doped with boron; and

said depositing said second semiconductor layer comprises epitaxial depositing silicon doped with phosphorous or arsenic.

12. The method according to claim 10, wherein doping said second semiconductor layer with said second type of impurity comprises implanting phosphorous or arsenic.

13. The method according to claim 10, wherein doping said first semiconductor layer with said first type of impurity comprises implanting boron.

14. The method according to claim 10, wherein doping a portion of said second semiconductor layer, opposite said first semiconductor layer, with said second type of impurity comprises implanting phosphorous.

15. The method according to claim 10, wherein forming said silicide comprises:

sputtering a metal film along said semiconductor substrate and said first semiconductor layer in said plurality of openings; and

thermal cycling said metal film said semiconductor substrate and said first semiconductor layer.

16. The method according to claim 10, further comprising:

depositing a second polysilicon layer in said first plurality of trenches between said first polysilicon layer and said second dielectric layer; and

forming a fourth dielectric layer between said first polysilicon layer and second polysilicon layer.