Method for reduced N+ diffusion in strained Si on SiGe substrate
First Claim
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1. A semiconductor device comprising:
- a relaxed SiGe-based substrate;
a tensile biaxially strained Si cap layer formed on the relaxed SiGe-based substrate;
a gate electrode formed on the relaxed SiGe-based substrate with a gate oxide formed on the Si cap layer;
source and drain extension regions formed in an upper surface of the SiGe substrate and containing an N type impurity; and
a low vacancy region that overlap the source and drain extension regions and containing an interstitial element or a vacancy-trapping element,wherein an implant profile of the interstitial element or the vacancy-trapping element fully contains an N type impurity profile, whereby diffusion retardation is maximized.
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Abstract
The first source and drain regions are formed in an upper surface of a SiGe substrate. The first source and drain regions containing an N type impurity. Vacancy concentration in the first source and drain regions are reduced in order to reduce diffusion of the N type impurity contained in the first source and drain regions. The vacancy concentration is reduced by an interstitial element or a vacancy-trapping element in the first source and drain regions. The interstitial element or the vacancy-trapping element is provided by ion-implantation.
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Citations
17 Claims
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1. A semiconductor device comprising:
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a relaxed SiGe-based substrate; a tensile biaxially strained Si cap layer formed on the relaxed SiGe-based substrate; a gate electrode formed on the relaxed SiGe-based substrate with a gate oxide formed on the Si cap layer; source and drain extension regions formed in an upper surface of the SiGe substrate and containing an N type impurity; and a low vacancy region that overlap the source and drain extension regions and containing an interstitial element or a vacancy-trapping element, wherein an implant profile of the interstitial element or the vacancy-trapping element fully contains an N type impurity profile, whereby diffusion retardation is maximized. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor device comprising:
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a relaxed SiGe-based substrate; a tensile biaxially strained Si cap layer formed on the relaxed SiGe-based substrate and which matches a lattice of the relaxed SiGe-based substrate; a gate electrode formed on the SiGe-based substrate with a gate oxide therebetween; source and drain extension regions formed in a surface of the relaxed SiGe substrate and containing an N type impurity; and low vacancy regions, containing an interstitial element or a vacancy-trapping element, formed in the source and drain extension regions, wherein an implant profile of the interstitial element or the vacancy-trapping element fully contains an N type impurity profile, whereby diffusion retardation is maximized. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A semiconductor device comprising:
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a relaxed SiGe-based substrate; a gate electrode formed on the SiGe-based substrate with a gate oxide therebetween; source and drain extension regions formed in an upper surface of the SiGe substrate and containing an N type impurity; and low vacancy regions, containing an interstitial element or a vacancy-trapping element, that substantially overlap the source and drain extension regions, wherein an implant profile of the interstitial element or the vacancy-trapping element fully contains an N type impurity profile, whereby diffusion retardation is maximized. - View Dependent Claims (14, 15, 16, 17)
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Specification