Method for reduced N+ diffusion in strained Si on SiGe substrate

• US 7,345,329 B2
• Filed: 02/15/2005
• Issued: 03/18/2008
• Est. Priority Date: 09/09/2003
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Chidambarrao, Dureseti, Dokumaci, Omer H.
• Primary Examiner(s): Pham; Long
• Application Number:
  US11/057,129
• Publication Number:
  US 20050145992A1
• Time in Patent Office: 1,127 Days
• Field of Search: 257/274, 257/279
• US Class Current: 257/279
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26566 of a cluster, e.g. using a gas cluster ion beam
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

The first source and drain regions are formed in an upper surface of a SiGe substrate. The first source and drain regions containing an N type impurity. Vacancy concentration in the first source and drain regions are reduced in order to reduce diffusion of the N type impurity contained in the first source and drain regions. The vacancy concentration is reduced by an interstitial element or a vacancy-trapping element in the first source and drain regions. The interstitial element or the vacancy-trapping element is provided by ion-implantation.

Claims

1. A semiconductor device comprising:

a relaxed SiGe-based substrate;

a tensile biaxially strained Si cap layer formed on the relaxed SiGe-based substrate;

a gate electrode formed on the relaxed SiGe-based substrate with a gate oxide formed on the Si cap layer;

source and drain extension regions formed in an upper surface of the SiGe substrate and containing an N type impurity; and

a low vacancy region that overlap the source and drain extension regions and containing an interstitial element or a vacancy-trapping element,

wherein an implant profile of the interstitial element or the vacancy-trapping element fully contains an N type impurity profile, whereby diffusion retardation is maximized.

2. The semiconductor device of claim 1, wherein the interstitial element is Si or O and the vacancy-trapping element is F, N, Xe, Ar, He, Kr or a noble gas element.

3. The semiconductor device of claim 1, wherein each of the interstitial element or the vacancy-trapping element is ion-implanted.

4. The semiconductor device of claim 1, wherein the semiconductor device is an N type device.

5. The semiconductor device of claim 1, wherein the N type impurity is ion-implanted in a self-aligned manner.

6. The semiconductor device of claim 1, wherein the vacancy-trapping element forms vacancy-based clusters.

7. A semiconductor device comprising:

a relaxed SiGe-based substrate;

a tensile biaxially strained Si cap layer formed on the relaxed SiGe-based substrate and which matches a lattice of the relaxed SiGe-based substrate;

a gate electrode formed on the SiGe-based substrate with a gate oxide therebetween;

source and drain extension regions formed in a surface of the relaxed SiGe substrate and containing an N type impurity; and

low vacancy regions, containing an interstitial element or a vacancy-trapping element, formed in the source and drain extension regions,

wherein an implant profile of the interstitial element or the vacancy-trapping element fully contains an N type impurity profile, whereby diffusion retardation is maximized.

8. The semiconductor device of claim 7, wherein the interstitial element is Si or O and the vacancy-trapping element is F, N, Xe, Ar, He, Kr or a noble gas element.

9. The semiconductor device of claim 7, wherein each of the interstitial element or the vacancy-trapping element is ion-implanted.

10. The semiconductor device of claim 7, wherein the semiconductor device is an N type device.

11. The semiconductor device of claim 7, wherein the N type impurity is ion-implanted in a self-aligned manner.

12. The semiconductor device of claim 7, wherein the vacancy-trapping element forms vacancy-based clusters.

13. A semiconductor device comprising:

a relaxed SiGe-based substrate;

a gate electrode formed on the SiGe-based substrate with a gate oxide therebetween;

source and drain extension regions formed in an upper surface of the SiGe substrate and containing an N type impurity; and

low vacancy regions, containing an interstitial element or a vacancy-trapping element, that substantially overlap the source and drain extension regions,

wherein an implant profile of the interstitial element or the vacancy-trapping element fully contains an N type impurity profile, whereby diffusion retardation is maximized.

14. The semiconductor device of claim 13, wherein the interstitial element is Si or O and the vacancy-trapping element is F, N, Xe, Ar, He, Kr or a noble gas element.

15. The semiconductor device of claim 13, wherein each of the interstitial element or the vacancy-trapping element is ion-implanted.

16. The semiconductor device of claim 13, wherein the semiconductor device is an N type device.

17. The semiconductor device of claim 13, wherein the N type impurity is ion-implanted in a self-aligned manner and the vacancy-trapping element forms vacancy-based clusters.