Wafer-level burn-in and test

• US 7,345,493 B2
• Filed: 07/18/2006
• Issued: 03/18/2008
• Est. Priority Date: 11/16/1993
• Status: Expired due to Fees

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Khandros, Igor Y., Pedersen, David V.
• Primary Examiner(s): HOLLINGTON, JERMELE M
• Application Number:
  US11/458,375
• Publication Number:
  US 20070013401A1
• Time in Patent Office: 609 Days
• Field of Search: None
• US Class Current: 324/750.05
• CPC Class Codes: G01R 31/287 Procedures; Software aspects
• CPC Class Codes: G01R 31/2874 related to temperature
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]

Abstract

Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. Physical alignment techniques are also described.

Claims

1. Method of performing burn-in on semiconductor devices, comprising:

electrically connecting first terminals of a test substrate to second terminals of at least one semiconductor device (DUT) by compressing a plurality of electrically conductive spring contact elements between the first terminals and the second terminals, wherein each of the conductive spring contact elements directly connects one of the first terminals to one of the second terminals;

powering up the at least one DUT;

maintaining the at least one DUT at a first temperature; and

maintaining the test substrate at a second temperature which is independent of the first temperature.

2. Method, according to claim 1, wherein:

the second temperature is lower than the first temperature.

3. Method, according to claim 1, wherein:

the second temperature is no greater than the first temperature.

4. Method, according to claim 1, further comprising:

disposing the test substrate and the at least one DUT in a vacuum environment, said vacuum providing a thermal barrier between the at least one DUT and the test substrate.

5. Method, according to claim 1, wherein:

the at least one DUT is a plurality of semiconductor devices resident on a semiconductor wafer (WUT).

6. Method, according to claim 1,

wherein the spring contact elements are mounted to the terminals of the test substrate.

7. Method, according to claim 1,

wherein the spring contact elements are mounted to the terminals of the at least one DUT.

8. Method, according to claim 7, wherein:

the spring contact elements are elongate, mounted by their bases to the at least one DUT, and have free ends; and

further comprising;

fanning out free ends of the spring contact elements so that they have a coarser pitch at their free ends than at their bases.