Programming memory devices
First Claim
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1. A method of programming a target memory cell of a memory device, comprising:
- applying a first voltage, at a first time, to a word line that includes the target memory cell;
applying a second voltage, at the first time, to word lines that do not include the target memory cell;
applying a third voltage, at the first time, to a bit line selectively coupled to a string of memory cells that includes the target memory cell;
increasing the first and second voltages at substantially the same rate, starting at a second time after the first time, until the first and second voltages reach a pass voltage level at a third time after the second time;
increasing the first voltage from the pass voltage, starting at the third time, to an initial programming voltage level at a fourth time after the third time;
maintaining the first voltage at the initial programming voltage level until a fifth time after the fourth time; and
determining whether the target memory cell is programmed after the fifth time; and
increasing the initial programming voltage level by a step voltage if it is determined that the target memory cell is not programmed;
wherein the initial programming voltage, the step voltage, the pass voltage, a length of time between the second and third times, and a length of time between the third and fifth times are each selectable after fabrication of the memory device.
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Abstract
A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.
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Citations
20 Claims
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1. A method of programming a target memory cell of a memory device, comprising:
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applying a first voltage, at a first time, to a word line that includes the target memory cell; applying a second voltage, at the first time, to word lines that do not include the target memory cell; applying a third voltage, at the first time, to a bit line selectively coupled to a string of memory cells that includes the target memory cell; increasing the first and second voltages at substantially the same rate, starting at a second time after the first time, until the first and second voltages reach a pass voltage level at a third time after the second time; increasing the first voltage from the pass voltage, starting at the third time, to an initial programming voltage level at a fourth time after the third time; maintaining the first voltage at the initial programming voltage level until a fifth time after the fourth time; and determining whether the target memory cell is programmed after the fifth time; and increasing the initial programming voltage level by a step voltage if it is determined that the target memory cell is not programmed; wherein the initial programming voltage, the step voltage, the pass voltage, a length of time between the second and third times, and a length of time between the third and fifth times are each selectable after fabrication of the memory device. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of programming a memory device, comprising:
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applying a first voltage, at a first time, to a first word line that includes a plurality of memory cells to be programmed; applying a second voltage, at the first time, to second word lines that include memory cells not to be programmed; applying a third voltage, at the first time, to one or more first bit lines selectively coupled to the first word line and the second word lines for programming one or more first memory cells, of the plurality of memory cells of the first word line to be programmed, at a first logic level; applying a fourth voltage, at the first time, to one or more second bit lines selectively coupled to the first word line and the second word lines for programming one or more second memory cells, of the plurality of memory cells of the first word line to be programmed, at a second logic level; increasing the first and second voltages at substantially the same rate, starting at a second time after the first time, until the first and second voltages reach a pass voltage level at a third time after the second time; increasing the first voltage from the pass voltage, starting at the third time, to an initial programming voltage level at a fourth time after the third time; maintaining the first voltage at the initial programming voltage level until a fifth time after the fourth time; and determining whether the one or more first memory cells are programmed at the first logic level after the fifth time; and increasing the initial programming voltage level by a step voltage if it is determined that the one or more first memory cells are not programmed at the first logic level; wherein the initial programming voltage, the step voltage, the pass voltage, a length of time between the second and third times, and a length of time between the third and fifth times are each selectable after fabrication of the memory device. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A NAND memory device comprising:
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a memory array comprising; a plurality of rows of memory cells, each row connected to a word line; and a plurality of columns of NAND strings of memory cells, each NAND string selectively connected to a bit line through a drain select gate of the respective column and to a source line through a source select gate of the respective column; control circuitry coupled to the memory array, the control circuitry adapted to perform a method for programming a target memory cell of the memory array, comprising; applying a first voltage, at a first time, to a word line that includes the target memory cell; applying a second voltage, at the first time, to word lines that do not include the target memory cell; increasing the first and second voltages at substantially the same rate, starting at a second time after the first time, until the first and second voltages reach a pass voltage level at a third time after the second time; increasing the first voltage from the pass voltage, starting at the third time, to an initial programming voltage level at a fourth time after the third time; maintaining the first voltage at the initial programming voltage level until a fifth time after the fourth time; determining whether the target memory cell is programmed after the fifth time; and increasing the initial programming voltage level by a step voltage if it is determined that the target memory cell is not programmed; a first register for storing a value corresponding to the pass voltage level, the first register programmable after fabrication and coupled to the control circuitry; a second register for storing a value corresponding to the initial programming level, the second register programmable after fabrication and coupled to the control circuitry; a third register for storing a value corresponding to the voltage step, the third register programmable after fabrication and coupled to the control circuitry; a fourth register for storing a value corresponding to the length of time between the second and third times, the fourth register programmable after fabrication and coupled to the control circuitry; and a fifth register for storing a value corresponding to a length of time between the third and fifth times, the fifth register programmable after fabrication and coupled to the control circuitry. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification