Data recovery methods in multi-state memory after program fail

• US 7,345,928 B2
• Filed: 12/14/2005
• Issued: 03/18/2008
• Est. Priority Date: 12/14/2004
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Li, Yan
• Primary Examiner(s): Phung; Anh
• Assistant Examiner(s): LE, TOAN K
• Application Number:
  US11/304,783
• Publication Number:
  US 20060126393A1
• Time in Patent Office: 825 Days
• Field of Search: 365/189.01, 365/185.21, 365/185.22, 365/189.05, 365/185.01
• US Class Current: 365/189.05
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A non-volatile memory device includes the ability to recover data in event of a program failure without having to maintain a copy of the data until the write is completed. As the integrity of the data can thus be maintained with having to save a copy, buffers can be freed up for other data or even eliminated, reducing the amount of controller space that needs to devoted data buffering. In exemplary embodiments, the data is recovered by logically combining the verify data for the (failed) write process maintained in data latches with the results of one or more read operations to reconstitute the data. The exemplary embodiments are for memory cells storing multi-state data, both in the format of independent upper page, lower page form, as well as in 2-bit form. This can be accomplished by a state machine and data latches in the sense amp area on the memory, without use of the controller.

Claims

1. A method of operating a non-volatile memory, comprising:

performing a program operation on one or more non-volatile memory cells to write a corresponding target data state to each of said memory cells, said program operation including maintaining verify data indicating whether each of said memory cells has been written to its respective target data state in one or more data latches corresponding to each of said memory cells;

determining whether the program operation has failed to successfully verify one or more of said memory cells as written to its target data state; and

in response to determining that the program operation has failed, performing a data recovery operation, the data recovery operation including;

performing one or more sensing operations on said memory cells; and

logically combining the results of the said sensing operations with the verify data maintained in said memory latches to recover the corresponding target data state of each of said memory cells.

2. The method of claim 1, wherein said non-volatile memory is part of a memory system including a controller and said non-volatile memory and said target data is not maintained in said controller subsequent to said performing a program operation.

3. The method of claim 2, wherein said target data is not maintained in the memory independently of said verify data.

4. The method of claim 1, wherein said memory cells are multi-state memory cells.

5. The method of claim 4, wherein said memory stores multi-state data in an upper page, lower page format and said program operation is to write upper page target data to said memory cells.

6. The method of claim 5, wherein lower page data has been written to said memory cells prior to said program operation to write upper page target data to said memory cells.

7. The method of claim 6, wherein said program operation further comprises reading said lower page data into said data latches prior to writing the upper page target data to said memory cells.

8. The method of claim 5, wherein said data recovery operation recovers both the lower page data and upper page target data.

9. The method of claim 4, wherein said method further comprises:

subsequent to said data recovery operation, programming the lower page data and upper page target data concurrently to another location in the memory.

10. In a memory system having a non-volatile array including a plurality of multi-state memory cells storing data as separate logical pages, a method comprising:

writing a first logical page of data to a first physical page of the array, where writing the first logical page includes writing memory cells to an intermediate data state;

storing data for a second logical page of data for each cell in the first physical page in a corresponding first data latch; and

performing a program operation to write the second logical page of data to said first physical page, wherein programming the second logical page includes further programming of the first logical page data from the intermediate state, the program operation to write a second logical page of data including;

reading the first logical page data from the first physical page, the first page data of each cell in the first physical page being stored in a corresponding second data latch;

programming the first physical page according to the content of the first and second data latches; and

subsequent to the data in the first latches verifying and prior to the data in the second data latches beginning to verify, copying out the second data latch content.

11. The method of claim 10, further comprising:

determining whether the operation to write the second logical page of data to said first physical page has failed to successfully verify one or more of said memory cells according to the content of the corresponding first and second data latches; and

in response to determining that the operation to write the second logical page of data to said first physical page has failed, writing the copied content of the second data latches to a second physical page.

12. In a memory system having a non-volatile array including a plurality of multi-state memory cells storing data as separate logical pages, a method comprising:

writing a first logical page of data to a first physical page of the array, where writing the first logical page includes writing memory cells to an intermediate data state;

storing data for a second logical page of data for each cell in the first physical page in a corresponding first data latch; and

performing a program operation to write the second logical page of data to said first physical page, wherein programming the second logical page includes further programming of the first logical page data from the intermediate state, the program operation to write a second logical page of data including;

reading the first logical page data from the first physical page, the first page data of each cell in the first physical page being stored in a corresponding second data latch and in a corresponding third data latch; and

programming the first physical page according to the content of the first and second latches while maintaining the copy of the first page data of each cell in the first physical page in the corresponding third data latch.

13. The method of claim 12, further comprising:

determining whether the operation to write the second logical page of data to said first physical page has failed to successfully verify one or more of said memory cells according to the content of the corresponding first and second data latches; and

in response to determining that the operation to write the second logical page of data to said first physical page has failed, copying the content of the third data latches to a second physical page.