Spread spectrum clock generator with controlled delay elements

• US 7,346,095 B1
• Filed: 02/20/2004
• Issued: 03/18/2008
• Est. Priority Date: 02/20/2004
• Status: Active Grant

• Current Assignee: IXYS Intl Limited (Littelfuse Incorporated)
• Original Assignee: ZiLOG Incorporated (Littelfuse Incorporated)
• Inventors: Hattori, Hide
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US10/783,338
• Time in Patent Office: 1,488 Days
• Field of Search: 375/130, 375/139, 375/239, 375/354, 375/364, 710/23, 710/25, 710/26, 711/109, 713/400, 713/401, 713500-502, 713/600, 713/601
• US Class Current: 375/130
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04B 2215/067 by modulation dispersion

Abstract

A programmable spread spectrum clock generator (SSCG) reduces electromagnetic interference by spreading the frequency bandwidth of an output signal. The rate at which the frequency of the output signal changes, as well as other aspects of the output signal, are software programmable. The programmable SSCG receives a periodic signal whose cycles have substantially identical periods and outputs the output signal whose cycles have periods that vary smoothly over a plurality of cycles of the periodic signal. The programmable SSCG generates a control signal using the periodic signal. The programmable SSCG includes a variable delay element that generates the output signal by delaying the periods of the periodic signal based on the magnitude of the control signal. The output signal is generated without using a phase locked loop. Moreover, successive cycles of the output signal rarely have identical periods.

Claims

1. A method comprising:

(a) receiving a periodic signal, the periodic signal having periodic signal cycles with corresponding time durations, wherein the time durations of the periodic signal cycles are substantially identical;

(b) generating a control signal having a magnitude, the magnitude of the control signal varying smoothly over a plurality of the periodic signal cycles; and

(c) delaying the periodic signal and thereby generating an output signal, wherein the output signal has output signal cycles with corresponding time durations, and wherein each of the time durations of the output signal cycles is a function of the magnitude of the control signal during the time duration.

2. The method of claim 1, wherein the delaying in (c) is performed by a variable delay element.

3. The method of claim 1, wherein the magnitude of the control signal is a current magnitude.

4. The method of claim 1, wherein the periodic signal is received from an external oscillator.

5. The method of claim 1, wherein the output signal is a spread spectrum clock signal.

6. The method of claim 1, wherein the output signal is generated without using a phase locked loop.

7. The method of claim 1, wherein the magnitude of the control signal increases exponentially over the plurality of the periodic signal cycles.

8. The method of claim 1, wherein the magnitude of the control signal varies in a quasi-sinusoidal manner over the plurality of the periodic signal cycles.

9. The method of claim 1, further comprising, between (a) and (b):

(d) generating an intermediary signal with a magnitude, wherein the magnitude of the intermediary signal varies substantially linearly over the plurality of the periodic signal cycles and is generated by an analog integrator, and wherein the magnitude of the control signal varies in substantially an exponential manner over the plurality of the periodic signal cycles.

10. The method of claim 9, wherein a non-linear signal is generated from the intermediary signal by a non-linear signal generator, and wherein the control signal is generated from the non-linear signal by a current mirror.

11. The method of claim 1, wherein each of the output signal cycles has a leading edge, wherein the time durations of the output signal cycles are bounded by leading edges of adjacent output signal cycles, wherein the output signal has a frequency that varies smoothly over a plurality of the output signal cycles, and wherein the frequency of the output signal is the reciprocal of the time durations of the output signal cycles.

12. A method comprising:

(a) supplying a periodic signal onto a data input lead of a variable delay element, the variable delay element also having a data output lead and a control input lead, wherein a propagation delay through the variable delay element from the data input lead to the data output lead varies as a function of a magnitude of a control signal on the control input lead; and

(b) varying the magnitude of the control signal smoothly over a length of time that encompasses a plurality of cycles of the periodic signal, the varying of the magnitude of the control signal causing an output signal to vary smoothly in frequency over the length of time, the output signal being output onto the data output lead.

13. The method of claim 12, wherein the magnitude of the control signal increases exponentially over the length of time.

14. The method of claim 12, wherein the magnitude of the control signal varies in a quasi-sinusoidal manner over the length of time.

15. The method of claim 12, wherein the magnitude of the control signal is a voltage magnitude.

16. The method of claim 12, further comprising:

(c) generating the control signal by dividing the periodic signal.

17. A device comprising:

a counter portion that receives a periodic signal and outputs a divided signal, the periodic signal having periodic signal cycles with corresponding time durations;

an integrator that receives the divided signal and outputs a signal having a magnitude; and

a variable delay element that receives the periodic signal and outputs an output signal, wherein the output signal has output signal cycles with corresponding time durations, and wherein each of the time durations of the output signal cycles is a function of the magnitude of the signal output by the integrator during the time duration.

18. The device of claim 17, further comprising:

a non-linear signal generator that receives the signal output by the integrator and generates a non-linear signal having a magnitude, wherein each of the time durations of the output signal cycles is a function of the magnitude of the non-linear signal during the time duration.

19. The device of claim 18, wherein the magnitude of the non-linear signal is a voltage magnitude.

20. The device of claim 17, wherein the variable delay element receives a control signal having a magnitude, and wherein each of the time durations of the output signal cycles is substantially proportional to the magnitude of the control signal during the time duration.

21. The device of claim 20, wherein the magnitude of the control signal is a current magnitude.

22. A device comprising:

a counter portion that receives a periodic signal having periodic signal cycles with corresponding time durations; and

means for generating (i) a control signal having a magnitude that varies smoothly over a plurality of the periodic signal cycles and (ii) an output signal having output signal cycles with corresponding time durations, wherein the output signal is generated by delaying the periodic signal, and wherein each of the time durations of the output signal cycles is proportional to the magnitude of the control signal during the time duration.

23. The device of claim 22, wherein the magnitude of the control signal is a current magnitude.

24. The device of claim 22, wherein the means does not include a phase locked loop.

25. The device of claim 22, wherein the output signal is a spread spectrum clock signal.

26. The device of claim 22, wherein each of the output signal cycles has a leading edge, wherein the time durations of the output signal cycles are bounded by leading edges of adjacent output signal cycles, wherein the output signal has a frequency that varies smoothly over a plurality of the output signal cycles, and wherein the frequency of the output signal is the reciprocal of the time durations of the output signal cycles.

27. A device comprising:

a variable delay element that receives a periodic signal and a control signal and outputs an output signal, wherein the periodic signal has a periodic signal cycle with a corresponding time duration, wherein the control signal has a control signal cycle with a corresponding time duration, a corresponding slope and a corresponding DC offset, wherein the output signal has an output signal cycle with a corresponding time duration, and wherein the time duration of the output signal cycle is a function of the time duration, the slope and the DC offset of the control signal during the time duration of the periodic signal cycle; and

a programmable spread spectrum control register with a first plurality of bits, a second plurality of bits and a third plurality of bits, wherein the first plurality of bits controls the DC offset of the control signal cycle, the second plurality of bits controls the slope of the control signal cycle, and the third plurality of bits controls the time duration of the control signal cycle.

28. The device of claim 27, further comprising:

a counter portion that receives the periodic signal.

29. The device of claim 27, wherein the control signal is generated by dividing the periodic signal.

30. The device of claim 27, wherein the periodic signal cycle is one of a plurality of periodic signal cycles, wherein the control signal has a magnitude, and wherein the magnitude of the control signal varies smoothly over the plurality of the periodic signal cycles.

31. The device of claim 30, wherein the magnitude of the control signal is a function of the time duration, the slope and the DC offset of the control signal.

32. The device of claim 27, wherein upon powering up the device, the first plurality of bits, the second plurality of bits and the third plurality of bits are set such that the time duration of the output signal cycle is substantially identical to the time duration of the periodic signal cycle.

33. The device of claim 27, wherein the device does not include a phase locked loop.