System for identification of defects on circuits or other arrayed products

• US 7,346,470 B2
• Filed: 06/10/2003
• Issued: 03/18/2008
• Est. Priority Date: 06/10/2003
• Status: Expired due to Term

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Wisniewski, Mary, Yashchin, Emmanuel, Trapp, Brian, Takken, Asya, Landers, Christina
• Primary Examiner(s): WEST, JEFFREY R
• Application Number:
  US10/459,132
• Publication Number:
  US 20040254752A1
• Time in Patent Office: 1,743 Days
• Field of Search: 702 81- 84, 702/117, 702/118, 702/179, 702181-183, 702/185, 382/145, 382/149, 716/4.W
• US Class Current: 702/181
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

A system and method is disclosed for assessing a probability of failure of operation of a semiconductor wafer. The method includes inputting risk factor data into a memory and inputting a plurality of wafers into a semiconductor fabrication manufacturing process. A subset of wafers is selected to obtain a sample population and at least one region of each wafer of the sample population is inspected. Circuit design data associated with each wafer of the sample population is obtained and one or more defects that present an increased risk to the operation of a particular wafer are identified. The identification is a function of the risk factor data, the inspecting step and the circuit design data. A probability of semiconductor wafer failure is calculated.

Claims

1. A method comprising:

obtaining circuit design data for at least one mask level;

correlating design shapes of the circuit design data to the at least one mask level;

from the correlated design shapes, generating a risk map for the at least one mask level that identifies risk factors specific to locations of the design shapes;

defining a statistical model that determines, for any individual defect, a probability that the individual defect will render a chip inoperable as a function of defect parameters and value of a risk factor of the risk map corresponding to a location of the individual defect;

measuring defects and their parameters and locations on the at least one mask level of selected chips;

measuring operability of the selected chips;

fitting the statistical model to the measured defect parameters, corresponding values of risk factors of the risk map, and measured chip operability;

from the fitted statistical model, determining a probability of a chip made from the circuit design data to be rendered inoperable; and

based on the determined probability, taking corrective action on the chip or its fabrication process.

2. The method of claim 1, wherein the statistical model comprises a separate risk map for each mask level of the chip.

3. The method of claim 1, wherein the statistical model comprises a risk map for only a single mask level.

4. The method of claim 1, wherein the defect parameters include defect size and defect classification.

5. The method of claim 1, wherein generating the risk map comprises using historical failure analysis data, said historical failure analysis data comprising a list of defects that were established as a cause of chip failure, and information regarding at least one selected parameter of a plurality of parameters of defects in the list that were established as a cause of chip failure.

6. The method of claim 1, further comprising, after determining the probability of a chip made from the circuit design data to be rendered inoperable:

measuring the chip for operability; and

updating the statistical model using the results of measuring the chip for operability when said results disagree with the determined probability of the chip being rendered inoperable.

7. The method of claim 1, wherein at least one of the design shapes is defined by a critical area.

8. The method of claim 1, wherein at least one of the design shapes is defined at least in part by a metal fraction of the chip.

9. The method of claim 1, wherein at least one of the design shapes is defined by a circuit that overlaps one of the measured defect locations.

10. The method of claim 1, wherein the corrective action comprises further inspecting the chip.

11. The method of claim 1, wherein measuring defects comprises preferentially inspecting locations of the selected chips corresponding to elevated risk factors to discover defects.

12. A computer readable medium embodying a computer program adapted to execute actions for evaluating a chip, the actions comprising:

receiving circuit design data for at least one mask level;

correlating design shapes of the circuit design data to the at least one mask level;

from the correlated design shapes, generating a risk map for the at least one mask level that identifies risk factors specific to locations of the design shapes;

defining a statistical model that determines, for any individual defect, a probability that the individual defect will render a chip inoperable as a function of defect parameters and value of a risk factor of the risk map corresponding to a location of the individual defect;

using measured defects and their parameters and locations on selected chips, fitting the statistical model to the measured defect parameters, corresponding values of the risk factors of the risk map, and measured operability of the selected chips;

from the fitted statistical model, determining a probability of a chip made from the circuit design data to be rendered inoperable; and

based on the determined probability, outputting a list of corrective action to be taken on the chip or on its fabrication process.

13. The computer readable medium of claim 12, wherein the statistical model comprises a separate risk map for each mask level of the chip.

14. The computer readable medium of claim 12, wherein the statistical model comprises a risk map for only a single mask level.

15. The computer readable medium of claim 12, wherein the defect-parameters include defect size and defect classification.

16. The computer readable medium of claim 12, wherein generating the risk map comprises using historical failure analysis data accessible by the computer program, said historical failure analysis data comprising a list of any defects that were established as a cause of chip failure, and information regarding at least one selected parameter of a plurality of parameters of any defects in the list that were established as a cause of chip failure.

17. The computer readable medium of claim 12, further comprising, after determining the probability of a chip made from the circuit design data to be rendered inoperable:

updating the statistical model using results of measuring the chip for operability when said results disagree with the determined probability.

18. The computer readable medium of claim 12, wherein at least one of the design shapes is defined by a critical area.

19. The computer readable medium of claim 12, wherein at least one of the design shapes is defined at least in part by a metal fraction of the chip.

20. The computer readable medium of claim 12, wherein at least one of the design shapes is defined by a circuit that overlaps one of the measured defect locations.

21. The computer readable medium of claim 12, wherein the list comprises preferential inspection locations on the chip.

22. The computer readable medium product of claim 12, wherein the measured defects arise from preferentially inspecting locations of the selected chips corresponding to elevated risk factors.