Arithmetic processor utilizing multi-table look up to obtain reciprocal operands

• US 7,346,642 B1
• Filed: 11/14/2003
• Issued: 03/18/2008
• Est. Priority Date: 11/14/2003
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Matula, David W., Briggs, Willard S.
• Primary Examiner(s): Mai; Tan V.
• Application Number:
  US10/714,554
• Time in Patent Office: 1,586 Days
• Field of Search: 708/500, 708/502, 708/605
• US Class Current: 708/497
• CPC Class Codes: G06F 1/02 Digital function generators
• CPC Class Codes: G06F 1/0356 by using two or more smaller tables, e.g. addressed by parts of the argument
• CPC Class Codes: G06F 2101/08 Powers or roots
• CPC Class Codes: G06F 2101/12 Reciprocal functions
• CPC Class Codes: G06F 2207/5356 Via reciprocal, i.e. calculate reciprocal only, or calculate reciprocal first and then the quotient from the reciprocal and the numerator
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/4873 Dividing
• CPC Class Codes: G06F 7/535 Dividing only
• CPC Class Codes: G06F 7/5525 Roots or inverse roots of single operands

Abstract

Methods for determining the square root, reciprocal square root, or reciprocal of a number performed by a processor of a computer system. The methods produce high precision estimates without using iterative steps. In addition, the methods taught herein utilize compressed tables for the coefficient terms A, B, and C from the quadratic expression Ax²+Bx+C, thus minimizing hardware requirements.

Claims

1. A system for evaluating a rounded arithmetic expression comprising:

a plurality of tables populated with values to generate a piecewise monotonic function;

an arithmetic unit comprising non-iterative logic coupled to the plurality of tables, the arithmetic unit comprising an input and an output, the input to receive an operand and the output to provide a floating point result for the arithmetic expression comprising an accuracy to a Unit in the Last Place (ULP);

a register comprising an input coupled to the output of the arithmetic unit.

2. The system of claim 1, wherein the arithmetic expression is a reciprocal.

3. The system of claim 1, wherein the arithmetic expression is a square root reciprocal.

4. The system of claim 1, wherein the arithmetic expression is a square root.

5. An arithmetic processor comprising:

a lookup table system including first, second and third component tables configured to provide a first operand, a second operand, a third operand, and a square operand;

a first multiplier comprising an input to receive at least a first portion of an input operand, the first multiplier further coupled to the first component table to multiply the first operand and a square operand to provide a first result, the square operand determined responsively to the first portion of the input operand;

a second multiplier comprising an input to receive at least a second portion of the input operand, the second multiplier further coupled to the second component table to multiply the second operand and a multiplier operand to provide a second result, the multiplier operand determined responsively to the second portion of the input operand; and

an adding circuit configured to add the first result and the second result and the third operand, the third operand determined responsive to a third portion of the input operand to provide a third result;

a rounding circuit coupled to receive the third result and to provide a rounded result accurate to a unit in the last place.

6. The arithmetic processor, as recited in claim 5, further comprising:

a square table configured to provide the square operand.

7. The arithmetic processor, as recited in claim 6, wherein the entries in the square table are stored in a Booth recoded format.

8. The arithmetic processor, as recited in claim 5, further comprising:

a Booth recoder configured to provide the multiplier operand.

9. The arithmetic processor, as recited in claim 5, wherein the arithmetic processor is configured to provide a reciprocal value of an input operand.

10. The arithmetic processor, as recited in claim 5, wherein the arithmetic processor is configured to provide a square root value of an input operand.

11. The arithmetic processor as recited in claim 5, wherein the arithmetic processor is configured to provide a square root reciprocal value of an input operand.

12. The arithmetic processor, as recited in claim 5, wherein the first portion of the input operand comprises high order bits of the input operand.

13. The arithmetic processor, as recited in claim 12, wherein the first and second portions of the input operand are mutually exclusive with each other.

14. The arithmetic processor, as recited in claim 13, wherein the first and third portions of the input operand are mutually exclusive with each other.

15. The arithmetic processor, as recited in claim 14, wherein the second and third portions of the input operand overlap with each other.