Method and apparatus for redundant location addressing using data compression
First Claim
1. A memory system, comprising:
- a first memory having addressable memory locations configured to store data;
a second memory having memory locations configured to store hash codes and decompressed addresses for addressable memory locations of the first memorya third memory having addressable memory locations configured to store data; and
a control circuit coupled to the first, second and third memories, the control circuit configured to generate a first hash code from a requested address to a memory location in the first memory and compare the first hash code to hash codes for decompressed addresses stored in the second memory, the control circuit further configured to determine whether an address stored in the second memory corresponds to the requested address in response to the first hash code matching a hash code for a decompressed address and access a memory location in the third memory in response to an address stored in the second memory corresponding to the requested address.
5 Assignments
0 Petitions
Accused Products
Abstract
A method and apparatus for identifying defective cells in a memory array includes receiving a request for accessing an address and analyzing the address to determine when the address matches an address stored in a temporary memory array. When the address does not match any address stored in the temporary memory array, a wait instruction is sent to a processor and the address is analyzed to determine which portion of compressed data stored in a map memory array to decompress. The map memory array stores data containing compressed addresses of defective cells in a first memory array. The portion of compressed data is then decompressed to provide expanded data when the address does not match any address stored in the temporary memory array. The expanded data are then written to the temporary memory array, and the expanded data are compared to the address to determine when the address corresponds to an expanded datum of the expanded data.
23 Citations
21 Claims
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1. A memory system, comprising:
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a first memory having addressable memory locations configured to store data; a second memory having memory locations configured to store hash codes and decompressed addresses for addressable memory locations of the first memory a third memory having addressable memory locations configured to store data; and a control circuit coupled to the first, second and third memories, the control circuit configured to generate a first hash code from a requested address to a memory location in the first memory and compare the first hash code to hash codes for decompressed addresses stored in the second memory, the control circuit further configured to determine whether an address stored in the second memory corresponds to the requested address in response to the first hash code matching a hash code for a decompressed address and access a memory location in the third memory in response to an address stored in the second memory corresponding to the requested address. - View Dependent Claims (2, 3, 4, 5)
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6. A memory system, comprising:
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a first memory having addressable memory locations; a second memory configured to store memory addresses corresponding to defective addressable memory locations in the first memory, the memory addresses stored in a compressed format having substitute address associated and stored with therewith; a third memory having addressable memory locations; and a control unit coupled to the first, second, and third memories, the control unit configured to decompress compressed memory addresses stored in the second memory and compare a memory address for an addressable memory location in the first memory to the decompressed memory addresses, the control unit further configured, in response to the memory address for the addressable memory location matching one of the decompressed memory addresses, to extract the substitute address associated with the matching decompressed memory address and access an addressable memory location in the third memory corresponding to the extracted substitute address rather than the addressable memory location in the first memory corresponding to the memory address. - View Dependent Claims (7, 8, 9, 10)
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11. A memory control circuit comprising:
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a control circuit configured to access memory arrays to retrieve data from a first memory array unit in response to memory access requests; a first memory array coupled to the control circuit and having memory cells configured to store data; a second memory array coupled to the control circuit and having memory cells to which defective memory cells of the first memory array are mapped; and a data compression circuit coupled to the control circuit and configured to compress data representing memory addresses corresponding to defective memory cells of the first memory array to provide compressed addresses and further configured to decompresses compressed addresses to provide decompressed addresses. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A computer comprising:
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a processor; a read-only memory configured to store instructions for operation of the processor; a random-access memory array configured to store data; a spare random-access memory array configured to store data corresponding to defective locations in the random-access memory array; a control circuit coupled to the processor, the read-only memory, the random-access memory and the spare random-access memory, the control circuit configured to access the read-only memory, the random-access memory and the spare random-access memory to retrieve data in response to commands from the processor; and a compression circuit coupled to the control circuit and configured to compress data indicative of addresses of defective storage locations in the random access memory array to provide compressed addresses and further configured to decompress the compressed addresses. - View Dependent Claims (19, 20, 21)
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Specification