Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow

• US 7,348,284 B2
• Filed: 08/10/2004
• Issued: 03/25/2008
• Est. Priority Date: 08/10/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Jin, Been-Yih, Datta, Suman, Chau, Robert, Zelick, Nancy M, Doyle, Brian S
• Primary Examiner(s): Vu; David
• Application Number:
  US10/915,780
• Publication Number:
  US 20060033095A1
• Time in Patent Office: 1,323 Days
• Field of Search: 438/154, 438/157, 438/158, 438/176, 438/199, 438/206, 438/212, 438/283, 438/752, 438/933, 257/192, 257/331, 257/369, 257/401, 257/616, 257/619, 257/E29.193
• US Class Current: 438/142
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure
• CPC Class Codes: Y10S 438/933 Germanium or silicon or Ge-Si on III-V

Abstract

A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si_1-x Ge_x layer is formed on the silicon-on-isolator (SOI) substrate. The relaxed Si_1-x Ge_x layer is patterned and subsequently etched to form a fin on the oxide. The compressively stressed Si_1-y Ge_y layer, having the Ge content y higher than the Ge content x in the relaxed Si_1-xGe_x layer, is epitaxially grown on the fin. The Si_1-y Ge_y layer covers the top and two sidewalls of the fin. The compressive stress in the Si_1-y Ge_y layer substantially increases the hole mobility in a channel of the non-planar tri-gate p-MOS transistor structure.

Claims

1. A method of forming a semiconductor structure, comprising:

forming an insulating layer;

forming a first layer that includes a first germanium content on the insulating layer, the first layer having a first lattice spacing, wherein the forming the first layer comprises

forming a third layer having a third germanium content over the insulating layer,

and forming a silicon layer on the third layer;

forming a fin having a top surface and opposing sidewalls from the first layer; and

forming a second layer that includes a second germanium content on the fin, wherein the second layer covers the top surface and the opposing sidewalls of the fin and has a second lattice spacing, which is larger than the first lattice spacing.

2. The method of claim 1, further comprising:

forming a gate dielectric layer on the second layer;

forming a gate electrode on the gate dielectric layer; and

forming a source region and a drain region on opposing sides of the gate electrode.

3. The method of claim 1, wherein forming the second layer on the fin comprises an epitaxial growth.

4. The method of claim 1, wherein the second layer covering the fin is under compressive stress.

5. The method of claim 1, wherein the first layer is a relaxed SiGe layer and the second layer is a compressively strained SiGe layer.

6. A method of forming a semiconductor transistor structure, comprising:

forming a first layer that includes a first germanium content on an insulating layer on a substrate, the first layer having a first lattice spacing, wherein the forming the first layer comprises

forming a third layer having a third germanium content over the insulating layer,

and forming a silicon layer on the third layer;

forming a first and a second fin from the first layer, the first fin being on a first portion and the second fin being on a second portion of a semiconductor transistor structure;

protecting a first portion of the semiconductor transistor structure with a first protective layer;

forming a second layer that includes a second germanium content having a second lattice spacing substantially larger than the first lattice spacing on the second fin;

removing the first protective layer from the first portion of the semiconductor transistor structure and protecting the second portion of the semiconductor transistor structure with a second protective layer; and

forming a fourth layer of a third material having a third lattice spacing substantially smaller than the first lattice spacing on the first fin.

7. The method of claim 6, further comprising:

forming gate dielectrics on the second layer and on the fourth layer of the third material;

forming gate electrodes on each of the gate dielectrics; and

forming a source region and a drain region at opposing sides of each of the first and the second gate electrodes.

8. The method of claim 6, wherein the second layer comprises silicon germanium and the third material comprises silicon.

9. The method of claim 6, wherein forming the second layer and the fourth layer comprises epitaxial growth.

10. The method of claim 9, wherein the second layer covers a top and two opposing sidewalls of the second fin and the fourth layer covers a top and two opposing sidewalls of the first fin.