Semiconductor device for high frequency uses and manufacturing method of the same

• US 7,348,630 B2
• Filed: 07/29/2004
• Issued: 03/25/2008
• Est. Priority Date: 02/13/2004
• Status: Expired due to Fees

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Yamauchi, Tsunenori, Nakamura, Shunji
• Primary Examiner(s): Gurley; Lynne
• Assistant Examiner(s): Gebremariam; Samuel A
• Application Number:
  US10/901,196
• Publication Number:
  US 20050179085A1
• Time in Patent Office: 1,335 Days
• Field of Search: 257/335, 257/344, 257/336, 257/337, 257/339, 257/E29.319
• US Class Current: 257/336
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

The semiconductor device has a semiconductor substrate, gate electrodes formed above the semiconductor substrate, and a pair of impurity diffusion layers formed in a surface layer of the semiconductor substrate at both sides of each of the gate electrodes. The semiconductor device also has drift layers formed in the surface layer of the semiconductor substrate between the gate electrodes and one of the impurity diffusion layers as a same conduction type as the impurity diffusion layers. The gate electrodes are made of metal including aluminum, and each is formed in an overhang shape. The semiconductor device can provide an LDMOS transistor enhanced in maximum transmission frequency and power gain and capable of a high-frequency operation with high efficiency as a basic element of a high-frequency power amplifier.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

gate electrodes formed above said semiconductor substrate;

a pair of impurity diffusion layers formed in a surface layer of said semiconductor substrate at both sides of each of said gate electrodes;

drift layers formed in the surface layer of said semiconductor substrate between said gate electrodes and one of said impurity diffusion layers as a same conduction type as said impurity diffusion layers; and

a pair of electrodes each electrically connected to the pair of impurity diffusion layers via a barrier metal film,

wherein said gate electrodes do not include said barrier metal film, and

wherein said gate electrodes have an upper portion extending over a side of a lower portion and made of metal including aluminum and silicon as a material.

2. The semiconductor device according to claim 1, further comprising:

a pair of electrodes formed above said semiconductor substrate to be connected to said respective impurity diffusion layers,

wherein each of said electrodes is formed of the same material as said gate electrodes.

3. The semiconductor device according to claim 2,

wherein said gate electrodes and said each electrode are formed so that lower parts of said electrodes are embedded in an interlayer insulating film formed above said semiconductor substrate, and

wherein said each electrode is formed with a metallic underlying film interposed between said each electrode and said interlayer insulating film, and said gate electrodes are formed to be in direct contact with the interlayer insulating film.

4. The semiconductor device according to claim 2, wherein shield layers formed of the same material as said gate electrodes to partition both the gate electrodes and one of said electrodes are included between said gate electrodes and one of said electrodes.

5. The semiconductor device according to claim 1, wherein an upper part of each of said gate electrodes is formed in an asymmetrical shape extending longer to a side of the one of said impurity diffusion layers on the other side.